1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 2f15cbe6fSPaul Mundt #ifndef __ASM_SH_SMC37C93X_H 3f15cbe6fSPaul Mundt #define __ASM_SH_SMC37C93X_H 4f15cbe6fSPaul Mundt 5f15cbe6fSPaul Mundt /* 6f15cbe6fSPaul Mundt * linux/include/asm-sh/smc37c93x.h 7f15cbe6fSPaul Mundt * 8f15cbe6fSPaul Mundt * Copyright (C) 2000 Kazumoto Kojima 9f15cbe6fSPaul Mundt * 10f15cbe6fSPaul Mundt * SMSC 37C93x Super IO Chip support 11f15cbe6fSPaul Mundt */ 12f15cbe6fSPaul Mundt 13f15cbe6fSPaul Mundt /* Default base I/O address */ 14f15cbe6fSPaul Mundt #define FDC_PRIMARY_BASE 0x3f0 15f15cbe6fSPaul Mundt #define IDE1_PRIMARY_BASE 0x1f0 16f15cbe6fSPaul Mundt #define IDE1_SECONDARY_BASE 0x170 17f15cbe6fSPaul Mundt #define PARPORT_PRIMARY_BASE 0x378 18f15cbe6fSPaul Mundt #define COM1_PRIMARY_BASE 0x2f8 19f15cbe6fSPaul Mundt #define COM2_PRIMARY_BASE 0x3f8 20f15cbe6fSPaul Mundt #define RTC_PRIMARY_BASE 0x070 21f15cbe6fSPaul Mundt #define KBC_PRIMARY_BASE 0x060 22f15cbe6fSPaul Mundt #define AUXIO_PRIMARY_BASE 0x000 /* XXX */ 23f15cbe6fSPaul Mundt 24f15cbe6fSPaul Mundt /* Logical device number */ 25f15cbe6fSPaul Mundt #define LDN_FDC 0 26f15cbe6fSPaul Mundt #define LDN_IDE1 1 27f15cbe6fSPaul Mundt #define LDN_IDE2 2 28f15cbe6fSPaul Mundt #define LDN_PARPORT 3 29f15cbe6fSPaul Mundt #define LDN_COM1 4 30f15cbe6fSPaul Mundt #define LDN_COM2 5 31f15cbe6fSPaul Mundt #define LDN_RTC 6 32f15cbe6fSPaul Mundt #define LDN_KBC 7 33f15cbe6fSPaul Mundt #define LDN_AUXIO 8 34f15cbe6fSPaul Mundt 35f15cbe6fSPaul Mundt /* Configuration port and key */ 36f15cbe6fSPaul Mundt #define CONFIG_PORT 0x3f0 37f15cbe6fSPaul Mundt #define INDEX_PORT CONFIG_PORT 38f15cbe6fSPaul Mundt #define DATA_PORT 0x3f1 39f15cbe6fSPaul Mundt #define CONFIG_ENTER 0x55 40f15cbe6fSPaul Mundt #define CONFIG_EXIT 0xaa 41f15cbe6fSPaul Mundt 42f15cbe6fSPaul Mundt /* Configuration index */ 43f15cbe6fSPaul Mundt #define CURRENT_LDN_INDEX 0x07 44f15cbe6fSPaul Mundt #define POWER_CONTROL_INDEX 0x22 45f15cbe6fSPaul Mundt #define ACTIVATE_INDEX 0x30 46f15cbe6fSPaul Mundt #define IO_BASE_HI_INDEX 0x60 47f15cbe6fSPaul Mundt #define IO_BASE_LO_INDEX 0x61 48f15cbe6fSPaul Mundt #define IRQ_SELECT_INDEX 0x70 49f15cbe6fSPaul Mundt #define DMA_SELECT_INDEX 0x74 50f15cbe6fSPaul Mundt 51f15cbe6fSPaul Mundt #define GPIO46_INDEX 0xc6 52f15cbe6fSPaul Mundt #define GPIO47_INDEX 0xc7 53f15cbe6fSPaul Mundt 54f15cbe6fSPaul Mundt /* UART stuff. Only for debugging. */ 55f15cbe6fSPaul Mundt /* UART Register */ 56f15cbe6fSPaul Mundt 57f15cbe6fSPaul Mundt #define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */ 58f15cbe6fSPaul Mundt #define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */ 59f15cbe6fSPaul Mundt #define UART_IER 0x2 /* Interrupt Enable Register */ 60f15cbe6fSPaul Mundt #define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */ 61f15cbe6fSPaul Mundt #define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ 62f15cbe6fSPaul Mundt #define UART_LCR 0x6 /* Line Control Register */ 63f15cbe6fSPaul Mundt #define UART_MCR 0x8 /* MODEM Control Register */ 64f15cbe6fSPaul Mundt #define UART_LSR 0xa /* Line Status Register */ 65f15cbe6fSPaul Mundt #define UART_MSR 0xc /* MODEM Status Register */ 66f15cbe6fSPaul Mundt #define UART_SCR 0xe /* Scratch Register */ 67f15cbe6fSPaul Mundt #define UART_DLL 0x0 /* Divisor Latch (LS) */ 68f15cbe6fSPaul Mundt #define UART_DLM 0x2 /* Divisor Latch (MS) */ 69f15cbe6fSPaul Mundt 70f15cbe6fSPaul Mundt #ifndef __ASSEMBLY__ 71f15cbe6fSPaul Mundt typedef struct uart_reg { 72f15cbe6fSPaul Mundt volatile __u16 rbr; 73f15cbe6fSPaul Mundt volatile __u16 ier; 74f15cbe6fSPaul Mundt volatile __u16 iir; 75f15cbe6fSPaul Mundt volatile __u16 lcr; 76f15cbe6fSPaul Mundt volatile __u16 mcr; 77f15cbe6fSPaul Mundt volatile __u16 lsr; 78f15cbe6fSPaul Mundt volatile __u16 msr; 79f15cbe6fSPaul Mundt volatile __u16 scr; 80f15cbe6fSPaul Mundt } uart_reg; 81f15cbe6fSPaul Mundt #endif /* ! __ASSEMBLY__ */ 82f15cbe6fSPaul Mundt 83f15cbe6fSPaul Mundt /* Alias for Write Only Register */ 84f15cbe6fSPaul Mundt 85f15cbe6fSPaul Mundt #define thr rbr 86f15cbe6fSPaul Mundt #define tcr iir 87f15cbe6fSPaul Mundt 88f15cbe6fSPaul Mundt /* Alias for Divisor Latch Register */ 89f15cbe6fSPaul Mundt 90f15cbe6fSPaul Mundt #define dll rbr 91f15cbe6fSPaul Mundt #define dlm ier 92f15cbe6fSPaul Mundt #define fcr iir 93f15cbe6fSPaul Mundt 94f15cbe6fSPaul Mundt /* Interrupt Enable Register */ 95f15cbe6fSPaul Mundt 96f15cbe6fSPaul Mundt #define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */ 97f15cbe6fSPaul Mundt #define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */ 98f15cbe6fSPaul Mundt #define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */ 99f15cbe6fSPaul Mundt #define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */ 100f15cbe6fSPaul Mundt 101f15cbe6fSPaul Mundt /* Interrupt Ident Register */ 102f15cbe6fSPaul Mundt 103f15cbe6fSPaul Mundt #define IIR_IP 0x0100 /* "0" if Interrupt Pending */ 104f15cbe6fSPaul Mundt #define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */ 105f15cbe6fSPaul Mundt #define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */ 106f15cbe6fSPaul Mundt #define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */ 107f15cbe6fSPaul Mundt #define IIR_FIFO 0xc000 /* FIFOs enabled */ 108f15cbe6fSPaul Mundt 109f15cbe6fSPaul Mundt /* FIFO Control Register */ 110f15cbe6fSPaul Mundt 111f15cbe6fSPaul Mundt #define FCR_FEN 0x0100 /* FIFO enable */ 112f15cbe6fSPaul Mundt #define FCR_RFRES 0x0200 /* Receiver FIFO reset */ 113f15cbe6fSPaul Mundt #define FCR_TFRES 0x0400 /* Transmitter FIFO reset */ 114f15cbe6fSPaul Mundt #define FCR_DMA 0x0800 /* DMA mode select */ 115*7dfaa9eaSFlavio Suligoi #define FCR_RTL 0x4000 /* Receiver trigger (LSB) */ 116*7dfaa9eaSFlavio Suligoi #define FCR_RTM 0x8000 /* Receiver trigger (MSB) */ 117f15cbe6fSPaul Mundt 118f15cbe6fSPaul Mundt /* Line Control Register */ 119f15cbe6fSPaul Mundt 120f15cbe6fSPaul Mundt #define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */ 121f15cbe6fSPaul Mundt #define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */ 122f15cbe6fSPaul Mundt #define LCR_STB 0x0400 /* Number of Stop Bits */ 123f15cbe6fSPaul Mundt #define LCR_PEN 0x0800 /* Parity Enable */ 124f15cbe6fSPaul Mundt #define LCR_EPS 0x1000 /* Even Parity Select */ 125f15cbe6fSPaul Mundt #define LCR_SP 0x2000 /* Stick Parity */ 126f15cbe6fSPaul Mundt #define LCR_SB 0x4000 /* Set Break */ 127f15cbe6fSPaul Mundt #define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ 128f15cbe6fSPaul Mundt 129f15cbe6fSPaul Mundt /* MODEM Control Register */ 130f15cbe6fSPaul Mundt 131f15cbe6fSPaul Mundt #define MCR_DTR 0x0100 /* Data Terminal Ready */ 132f15cbe6fSPaul Mundt #define MCR_RTS 0x0200 /* Request to Send */ 133f15cbe6fSPaul Mundt #define MCR_OUT1 0x0400 /* Out 1 */ 134f15cbe6fSPaul Mundt #define MCR_IRQEN 0x0800 /* IRQ Enable */ 135f15cbe6fSPaul Mundt #define MCR_LOOP 0x1000 /* Loop */ 136f15cbe6fSPaul Mundt 137f15cbe6fSPaul Mundt /* Line Status Register */ 138f15cbe6fSPaul Mundt 139f15cbe6fSPaul Mundt #define LSR_DR 0x0100 /* Data Ready */ 140f15cbe6fSPaul Mundt #define LSR_OE 0x0200 /* Overrun Error */ 141f15cbe6fSPaul Mundt #define LSR_PE 0x0400 /* Parity Error */ 142f15cbe6fSPaul Mundt #define LSR_FE 0x0800 /* Framing Error */ 143f15cbe6fSPaul Mundt #define LSR_BI 0x1000 /* Break Interrupt */ 144f15cbe6fSPaul Mundt #define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ 145f15cbe6fSPaul Mundt #define LSR_TEMT 0x4000 /* Transmitter Empty */ 146f15cbe6fSPaul Mundt #define LSR_FIFOE 0x8000 /* Receiver FIFO error */ 147f15cbe6fSPaul Mundt 148f15cbe6fSPaul Mundt /* MODEM Status Register */ 149f15cbe6fSPaul Mundt 150f15cbe6fSPaul Mundt #define MSR_DCTS 0x0100 /* Delta Clear to Send */ 151f15cbe6fSPaul Mundt #define MSR_DDSR 0x0200 /* Delta Data Set Ready */ 152f15cbe6fSPaul Mundt #define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ 153f15cbe6fSPaul Mundt #define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ 154f15cbe6fSPaul Mundt #define MSR_CTS 0x1000 /* Clear to Send */ 155f15cbe6fSPaul Mundt #define MSR_DSR 0x2000 /* Data Set Ready */ 156f15cbe6fSPaul Mundt #define MSR_RI 0x4000 /* Ring Indicator */ 157f15cbe6fSPaul Mundt #define MSR_DCD 0x8000 /* Data Carrier Detect */ 158f15cbe6fSPaul Mundt 159f15cbe6fSPaul Mundt /* Baud Rate Divisor */ 160f15cbe6fSPaul Mundt 161f15cbe6fSPaul Mundt #define UART_CLK (1843200) /* 1.8432 MHz */ 162f15cbe6fSPaul Mundt #define UART_BAUD(x) (UART_CLK / (16 * (x))) 163f15cbe6fSPaul Mundt 164f15cbe6fSPaul Mundt /* RTC register definition */ 165f15cbe6fSPaul Mundt #define RTC_SECONDS 0 166f15cbe6fSPaul Mundt #define RTC_SECONDS_ALARM 1 167f15cbe6fSPaul Mundt #define RTC_MINUTES 2 168f15cbe6fSPaul Mundt #define RTC_MINUTES_ALARM 3 169f15cbe6fSPaul Mundt #define RTC_HOURS 4 170f15cbe6fSPaul Mundt #define RTC_HOURS_ALARM 5 171f15cbe6fSPaul Mundt #define RTC_DAY_OF_WEEK 6 172f15cbe6fSPaul Mundt #define RTC_DAY_OF_MONTH 7 173f15cbe6fSPaul Mundt #define RTC_MONTH 8 174f15cbe6fSPaul Mundt #define RTC_YEAR 9 175f15cbe6fSPaul Mundt #define RTC_FREQ_SELECT 10 176f15cbe6fSPaul Mundt # define RTC_UIP 0x80 177f15cbe6fSPaul Mundt # define RTC_DIV_CTL 0x70 178f15cbe6fSPaul Mundt /* This RTC can work under 32.768KHz clock only. */ 179f15cbe6fSPaul Mundt # define RTC_OSC_ENABLE 0x20 180f15cbe6fSPaul Mundt # define RTC_OSC_DISABLE 0x00 181f15cbe6fSPaul Mundt #define RTC_CONTROL 11 182f15cbe6fSPaul Mundt # define RTC_SET 0x80 183f15cbe6fSPaul Mundt # define RTC_PIE 0x40 184f15cbe6fSPaul Mundt # define RTC_AIE 0x20 185f15cbe6fSPaul Mundt # define RTC_UIE 0x10 186f15cbe6fSPaul Mundt # define RTC_SQWE 0x08 187f15cbe6fSPaul Mundt # define RTC_DM_BINARY 0x04 188f15cbe6fSPaul Mundt # define RTC_24H 0x02 189f15cbe6fSPaul Mundt # define RTC_DST_EN 0x01 190f15cbe6fSPaul Mundt 191f15cbe6fSPaul Mundt #endif /* __ASM_SH_SMC37C93X_H */ 192