1 // SPDX-License-Identifier: GPL-2.0-only
32 #define SOFT_RSTZ_BIT		BIT(0)
33 #define CNT_EN_BIT		BIT(1)
34 #define WRAP_EN_BIT		BIT(2)
35 #define LOAD_EN_BIT		BIT(3)
36 #define READ_EN_BIT		BIT(4)
37 #define INT_MASK_BIT		BIT(5)
38 #define INT_FORCE_BIT		BIT(6)
39 #define INT_CLEAR_BIT		BIT(7)
42 #define RAW_INT_BIT		BIT(0)
43 #define ALM_INT_BIT		BIT(1)
55 	seconds = readw(priv->rtc_base + REG_RTC_MATCH_VAL_L)  in msc313_rtc_read_alarm()
56 			| ((unsigned long)readw(priv->rtc_base + REG_RTC_MATCH_VAL_H) << 16);  in msc313_rtc_read_alarm()
58 	rtc_time64_to_tm(seconds, &alarm->time);  in msc313_rtc_read_alarm()
60 	if (!(readw(priv->rtc_base + REG_RTC_CTRL) & INT_MASK_BIT))  in msc313_rtc_read_alarm()
61 		alarm->enabled = 1;  in msc313_rtc_read_alarm()
71 	reg = readw(priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_alarm_irq_enable()
76 	writew(reg, priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_alarm_irq_enable()
85 	seconds = rtc_tm_to_time64(&alarm->time);  in msc313_rtc_set_alarm()
86 	writew((seconds & 0xFFFF), priv->rtc_base + REG_RTC_MATCH_VAL_L);  in msc313_rtc_set_alarm()
87 	writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_MATCH_VAL_H);  in msc313_rtc_set_alarm()
89 	msc313_rtc_alarm_irq_enable(dev, alarm->enabled);  in msc313_rtc_set_alarm()
96 	return readw(priv->rtc_base + REG_RTC_CTRL) & CNT_EN_BIT;  in msc313_rtc_get_enabled()
103 	reg = readw(priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_set_enabled()
105 	writew(reg, priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_set_enabled()
115 		return -EINVAL;  in msc313_rtc_read_time()
117 	reg = readw(priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_read_time()
118 	writew(reg | READ_EN_BIT, priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_read_time()
120 	/* Wait for HW latch done */  in msc313_rtc_read_time()
121 	while (readw(priv->rtc_base + REG_RTC_CTRL) & READ_EN_BIT)  in msc313_rtc_read_time()
124 	seconds = readw(priv->rtc_base + REG_RTC_CNT_VAL_L)  in msc313_rtc_read_time()
125 			| ((unsigned long)readw(priv->rtc_base + REG_RTC_CNT_VAL_H) << 16);  in msc313_rtc_read_time()
139 	writew(seconds & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_L);  in msc313_rtc_set_time()
140 	writew((seconds >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_LOAD_VAL_H);  in msc313_rtc_set_time()
143 	reg = readw(priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_set_time()
144 	writew(reg | LOAD_EN_BIT, priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_set_time()
146 	/* Wait for HW latch done */  in msc313_rtc_set_time()
147 	while (readw(priv->rtc_base + REG_RTC_CTRL) & LOAD_EN_BIT)  in msc313_rtc_set_time()
166 	reg = readw(priv->rtc_base + REG_RTC_STATUS_INT);  in msc313_rtc_interrupt()
170 	reg = readw(priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_interrupt()
173 	writew(reg, priv->rtc_base + REG_RTC_CTRL);  in msc313_rtc_interrupt()
175 	rtc_update_irq(priv->rtc_dev, 1, RTC_IRQF | RTC_AF);  in msc313_rtc_interrupt()
182 	struct device *dev = &pdev->dev;  in msc313_rtc_probe()
189 	priv = devm_kzalloc(&pdev->dev, sizeof(struct msc313_rtc), GFP_KERNEL);  in msc313_rtc_probe()
191 		return -ENOMEM;  in msc313_rtc_probe()
193 	priv->rtc_base = devm_platform_ioremap_resource(pdev, 0);  in msc313_rtc_probe()
194 	if (IS_ERR(priv->rtc_base))  in msc313_rtc_probe()
195 		return PTR_ERR(priv->rtc_base);  in msc313_rtc_probe()
199 		return -EINVAL;  in msc313_rtc_probe()
201 	priv->rtc_dev = devm_rtc_allocate_device(dev);  in msc313_rtc_probe()
202 	if (IS_ERR(priv->rtc_dev))  in msc313_rtc_probe()
203 		return PTR_ERR(priv->rtc_dev);  in msc313_rtc_probe()
205 	priv->rtc_dev->ops = &msc313_rtc_ops;  in msc313_rtc_probe()
206 	priv->rtc_dev->range_max = U32_MAX;  in msc313_rtc_probe()
209 			       dev_name(&pdev->dev), &pdev->dev);  in msc313_rtc_probe()
222 	writew(rate & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_L);  in msc313_rtc_probe()
223 	writew((rate >> 16) & 0xFFFF, priv->rtc_base + REG_RTC_FREQ_CW_H);  in msc313_rtc_probe()
227 	return devm_rtc_register_device(priv->rtc_dev);  in msc313_rtc_probe()
231 	{ .compatible = "mstar,msc313-rtc" },
239 		.name = "msc313-rtc",