| /freebsd/sys/contrib/device-tree/Bindings/clock/ti/ |
| H A D | mux.txt | 4 register-mapped multiplexer with multiple input clock signals or
22 "index-starts-at-one" modified the scheme as follows:
34 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
37 - compatible : shall be "ti,mux-clock" or "ti,composite-mux-clock".
38 - #clock-cells : from common clock binding; shall be set to 0.
39 - clocks : link phandles of parent clocks
40 - reg : register offset for register controlling adjustable mux
43 - clock-output-names : from common clock binding.
44 - ti,bit-shift : number of bits to shift the bit-mask, defaults to
46 - ti,index-starts-at-one : valid input select programming starts at 1, not
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| H A D | ti,mux-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,mux-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock assumes a register-mapped multiplexer with multiple inpt clock
31 "index-starts-at-one" modified the scheme as follows:
46 - ti,mux-clock
47 - ti,composite-mux-clock
49 "#clock-cells":
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| H A D | divider.txt | 4 register-mapped adjustable clock rate divider that does not gate and has
15 ti,index-starts-at-one - valid divisor values start at 1, not the default
22 ti,index-power-of-two - valid divisor values are powers of two. E.g:
39 Any zero value in this array means the corresponding bit-value is invalid
50 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
54 - compatible : shall be "ti,divider-clock" or "ti,composite-divider-clock".
55 - #clock-cells : from common clock binding; shall be set to 0.
56 - clocks : link to phandle of parent clock
57 - reg : offset for register controlling adjustable divider
60 - clock-output-names : from common clock binding.
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| H A D | ti,divider-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tero Kristo <kristo@kernel.org>
13 This clock It assumes a register-mapped adjustable clock rate divider
25 ti,index-starts-at-one - valid divisor values start at 1, not the default
32 ti,index-power-of-two - valid divisor values are powers of two. E.g:
49 Any zero value in this array means the corresponding bit-value is invalid
61 - $ref: ti,autoidle.yaml#
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | fairchild,74hc595.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
15 the 74HC595 sees as a rising edge on the latch clock that results in a
21 latch clock * trigger
27 - Maxime Ripard <mripard@kernel.org>
32 - fairchild,74hc595
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| /freebsd/sys/amd64/vmm/io/ |
| H A D | vatpit.c | 1 /*-
52 #define VATPIT_LOCK(vatpit) mtx_lock_spin(&((vatpit)->mtx))
53 #define VATPIT_UNLOCK(vatpit) mtx_unlock_spin(&((vatpit)->mtx))
54 #define VATPIT_LOCKED(vatpit) mtx_owned(&((vatpit)->mtx))
114 bintime_sub(&delta, &c->now_bt); in vatpit_delta_ticks()
117 result += delta.frac / vatpit->freq_bt.frac; in vatpit_delta_ticks()
129 c = &vatpit->channel[channel]; in vatpit_get_out()
131 switch (c->mode) { in vatpit_get_out()
134 out = (delta_ticks >= c->initial); in vatpit_get_out()
152 vatpit = arg->vatpit; in vatpit_callout_handler()
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| /freebsd/sys/dev/ic/ |
| H A D | via6522reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
38 #define REG_T1CL 4 /* T1 low-order latch/low-order counter */
39 #define REG_T1CH 5 /* T1 high-order counter */
40 #define REG_T1LL 6 /* T1 low-order latches */
41 #define REG_T1LH 7 /* T1 high-order latches */
42 #define REG_T2CL 8 /* T2 low-order latch/low-order counter */
43 #define REG_T2CH 9 /* T2 high-order counter */
48 #define REG_IER 14 /* Interrupt-enable register */
54 #define ACR_SR_DIR 0x4 /* Bit for shift-register direction 1=out */
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| H A D | i8253reg.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
37 * This chip has three independent 16-bit down counters that can be
51 * you write a "latch" command into the mode register, then read the stable
75 #define TIMER_LATCH 0x00 /* latch counter for reading */
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | IVUsers.cpp | 1 //===- IVUsers.cpp - Induction Variable Users -------------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
22 #include "llvm/Config/llvm-config.h"
32 #define DEBUG_TYPE "iv-users"
42 INITIALIZE_PASS_BEGIN(IVUsersWrapperPass, "iv-users",
48 INITIALIZE_PASS_END(IVUsersWrapperPass, "iv-users", "Induction Variable Users", in INITIALIZE_PASS_DEPENDENCY()
53 /// isInteresting - Test whether the given expression is "interesting" when
60 // Keep things simple. Don't touch loop-variant strides unless they're in isInteresting()
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| H A D | IVDescriptors.cpp | 1 //===- llvm/Analysis/IVDescriptors.cpp - IndVar Descriptors -----*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
30 #define DEBUG_TYPE "iv-descriptors"
34 for (const Use &Use : I->operands()) in areAllUsesIn()
64 /// Determines if Phi may have been type-promoted. If Phi has a single user
66 /// account for the narrower bit width represented by the mask, and the AND
71 if (!Phi->hasOneUse()) in lookThroughAnd()
75 Instruction *I, *J = cast<Instruction>(Phi->use_begin()->getUser()); in lookThroughAnd()
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | dra76x.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
12 target-module@42c01900 {
13 compatible = "ti,sysc-dra7-mcan", "ti,sysc";
15 #address-cells = <1>;
16 #size-cells = <1>;
20 reg-names = "rev", "sysc", "syss";
21 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
23 ti,syss-mask = <1>;
25 clock-names = "fck";
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| /freebsd/sys/arm/ti/clk/ |
| H A D | ti_mux_clock.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
76 { "ti,mux-clock", TI_MUX_CLOCK },
77 { "ti,composite-mux-clock", TI_COMPOSITE_MUX_CLOCK },
87 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) in ti_mux_probe()
99 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk()
100 if (sc->clkdom == NULL) { in register_clk()
101 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk()
105 err = clknode_mux_register(sc->clkdom, &sc->mux_def); in register_clk()
107 DPRINTF(sc->sc_dev, "clknode_mux_register failed %x\n", err); in register_clk()
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| H A D | ti_divider_clock.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
74 { "ti,divider-clock", TI_DIVIDER_CLOCK },
75 { "ti,composite-divider-clock", TI_COMPOSITE_DIVIDER_CLOCK },
83 sc->clkdom = clkdom_create(sc->sc_dev); in register_clk()
84 if (sc->clkdom == NULL) { in register_clk()
85 DPRINTF(sc->sc_dev, "Failed to create clkdom\n"); in register_clk()
89 err = clknode_div_register(sc->clkdom, &sc->div_def); in register_clk()
91 DPRINTF(sc->sc_dev, "clknode_div_register failed %x\n", err); in register_clk()
95 err = clkdom_finit(sc->clkdom); in register_clk()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LoopPredication.cpp | 1 //===-- LoopPredication.cpp - Guard based loop predication pass -------
1139 auto *Latch = L->getLoopLatch(); predicateLoopExits() local
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| H A D | LoopFuse.cpp | 1 //===- LoopFuse.cpp - Loop Fusion Pass ------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
71 #define DEBUG_TYPE "loop-fusion"
79 STATISTIC(InvalidLatch, "Loop has invalid latch");
92 "Loop has a non-empty preheader with instructions that cannot be moved");
95 STATISTIC(NonEmptyExitBlock, "Candidate has a non-empty exit block with "
97 STATISTIC(NonEmptyGuardBlock, "Candidate has a non-empty guard block with "
112 "loop-fusion-dependence-analysis",
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| H A D | InductiveRangeCheckElimination.cpp | 1 //===- InductiveRangeCheckElimination.cpp - --------
596 BasicBlock *Latch = nullptr; global() member
902 BasicBlock *Latch = L.getLoopLatch(); parseLoopStructure() local
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| /freebsd/sys/contrib/device-tree/Bindings/iio/dac/ |
| H A D | microchip,mcp4821.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 +---------+--------------+-------------+
15 |---------|--------------|-------------|
16 | MCP4801 | 8-bit | 1 |
17 | MCP4802 | 8-bit | 2 |
18 | MCP4811 | 10-bit | 1 |
19 | MCP4812 | 10-bit | 2 |
20 | MCP4821 | 12-bit | 1 |
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1 //===- HexagonHardwareLoops.cpp - Identify and generate hardware loops ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 // zero-cycle overhead.
20 // - Countable loops (w/ ind. var for a trip count)
21 // - Assumes loops are normalized by IndVarSimplify
22 // - Try inner-most loops first
23 // - No function calls in loops.
25 //===----------------------------------------------------------------------===//
69 static cl::opt<int> HWLoopLimit("hexagon-max-hwloop", cl::Hidden, cl::init(-1));
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 For Intel LGM SoC - "intel,lgm-qspi", "cdns,qspi-nor".
9 - reg : Contains two entries, each of which is a tuple consisting of a
13 - interrupts : Unit interrupt specifier for the controller interrupt.
14 - clocks : phandle to the Quad SPI clock.
15 - cdns,fifo-depth : Size of the data FIFO in words.
16 - cdns,fifo-width : Bus width of the data FIFO in bytes.
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | cadence-quadspi.txt | 4 - compatible : should be one of the following:
5 Generic default - "cdns,qspi-nor".
6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
7 For TI AM654 SoC - "ti,am654-ospi", "cdns,qspi-nor".
8 - reg : Contains two entries, each of which is a tuple consisting of a
12 - interrupts : Unit interrupt specifier for the controller interrupt.
13 - clocks : phandle to the Quad SPI clock.
14 - cdns,fifo-depth : Size of the data FIFO in words.
15 - cdns,fifo-width : Bus width of the data FIFO in bytes.
16 - cdns,trigger-address : 32-bit indirect AHB trigger address.
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| /freebsd/sys/dev/aic7xxx/ |
| H A D | aic7xxx.seq | 1 /*-
4 * Copyright (c) 1994-2001 Justin T. Gibbs.
5 * Copyright (c) 2000-2001 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
58 * use byte 27 of the SCB as a pseudo-next pointer and to thread a list
59 * of SCBs that are awaiting selection. Since 0-0xfe are valid SCB indexes,
61 * this list every time a request sense occurs or after completing a non-tagged
76 if ((ahc->features & AHC_ULTRA2) != 0) {
80 if ((ahc->features & AHC_TWIN) != 0) {
88 if ((ahc->features & AHC_TWIN) != 0) {
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_pcie_interrupts.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
73 * App group A interrupts mask - don't change
84 * [RC only] Deassert_INTA received - there's a dedicated GIC interrupt
95 * [RC only] Assert_INTA received - there's a dedicated GIC interrupt
111 /** [RC only] PME Status bit assertion in the Root Status register With INTA */
113 /** [RC only] PME Status bit assertion in the Root Status register With MSI or MSIX enabled */
135 * App group B interrupts mask - don't change
154 * messages only, and latch the headers in registers
160 * messages only, and latch the headers in registers
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| H A D | al_hal_iofic_regs.h | 10 found at http://www.gnu.org/licenses/gpl-2.0.html
51 uint32_t int_cause_set_grp; /* Interrupt Cause Set RegisterWriting 1 to a bit in t ... */
53 uint32_t int_mask_grp; /* Interrupt Mask RegisterIf Auto-mask control bit =TR ... */
55 uint32_t int_mask_clear_grp; /* Interrupt Mask Clear RegisterUsed when auto-mask co ... */
57 uint32_t int_status_grp; /* Interrupt status RegisterThis register latch the st ... */
61 uint32_t int_abort_msk_grp; /* Interrupt Mask RegisterEach bit in this register ma ... */
63 uint32_t int_log_msk_grp; /* Interrupt Log RegisterEach bit in this register mas ... */
87 /* (must be set only when MSIX is enabled)When Auto-Ma ... */
89 /* Auto_Clear (RW)When Auto-Clear =1, the bits in the ... */
95 /* When mask_msi_x =1, No MSI-X from this group is sen ... */
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanHCFGBuilder.cpp | 1 //===-- VPlanHCFGBuilder.cpp ----------------------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This file implements the construction of a VPlan-based Hierarchical CFG
11 /// (H-CFG) for an incoming IR. This construction comprises the following
14 /// 1. PlainCFGBuilder class: builds a plain VPBasicBlock-based CFG that
22 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "loop-vectorize"
45 // Builder of the VPlan instruction-level representation.
49 // construction because subsequent VPlan-to-VPlan transformation may
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| /freebsd/share/man/man4/ |
| H A D | uart.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
72 EIA RS-232C (CCITT V.24) serial communications interface.
112 It contains the bus attachments and the low-level interrupt handler.
144 .Bl -bullet -compact
182 .Bl -tag -compact -offset "mmmm" -width "mmmm"
193 .Bl -tag -compact -offset "mmmm" -width "mmmm"
195 Invert the pulse (RS-232 logic low = ASSERT, high = CLEAR).
202 In narrow mode the driver uses the hardware's ability to latch a line
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