1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/clock/ti/ti,divider-clock.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Texas Instruments divider clock 8 9maintainers: 10 - Tero Kristo <kristo@kernel.org> 11 12description: | 13 This clock It assumes a register-mapped adjustable clock rate divider 14 that does not gate and has only one input clock or parent. By default the 15 value programmed into the register is one less than the actual divisor value. 16 E.g: 17 18 register value actual divisor value 19 0 1 20 1 2 21 2 3 22 23 This assumption may be modified by the following optional properties: 24 25 ti,index-starts-at-one - valid divisor values start at 1, not the default 26 of 0. E.g: 27 register value actual divisor value 28 1 1 29 2 2 30 3 3 31 32 ti,index-power-of-two - valid divisor values are powers of two. E.g: 33 register value actual divisor value 34 0 1 35 1 2 36 2 4 37 38 Additionally an array of valid dividers may be supplied like so: 39 40 ti,dividers = <4>, <8>, <0>, <16>; 41 42 Which will map the resulting values to a divisor table by their index: 43 register value actual divisor value 44 0 4 45 1 8 46 2 <invalid divisor, skipped> 47 3 16 48 49 Any zero value in this array means the corresponding bit-value is invalid 50 and must not be used. 51 52 The binding must also provide the register to control the divider and 53 unless the divider array is provided, min and max dividers. Optionally 54 the number of bits to shift that mask, if necessary. If the shift value 55 is missing it is the same as supplying a zero shift. 56 57 This binding can also optionally provide support to the hardware autoidle 58 feature. 59 60allOf: 61 - $ref: ti,autoidle.yaml# 62 63properties: 64 compatible: 65 enum: 66 - ti,divider-clock 67 - ti,composite-divider-clock 68 69 "#clock-cells": 70 const: 0 71 72 clocks: 73 maxItems: 1 74 75 clock-output-names: 76 maxItems: 1 77 78 reg: 79 maxItems: 1 80 81 ti,dividers: 82 $ref: /schemas/types.yaml#/definitions/uint32-array 83 description: 84 array of integers defining divisors 85 86 ti,bit-shift: 87 $ref: /schemas/types.yaml#/definitions/uint32 88 description: 89 number of bits to shift the divider value 90 maximum: 31 91 default: 0 92 93 ti,min-div: 94 $ref: /schemas/types.yaml#/definitions/uint32 95 description: 96 min divisor for dividing the input clock rate, only 97 needed if the first divisor is offset from the default value (1) 98 minimum: 1 99 default: 1 100 101 ti,max-div: 102 $ref: /schemas/types.yaml#/definitions/uint32 103 description: 104 max divisor for dividing the input clock rate, only needed 105 if ti,dividers is not defined. 106 107 ti,index-starts-at-one: 108 type: boolean 109 description: 110 valid divisor programming starts at 1, not zero, 111 only valid if ti,dividers is not defined 112 113 ti,index-power-of-two: 114 type: boolean 115 description: 116 valid divisor programming must be a power of two, 117 only valid if ti,dividers is not defined. 118 119 ti,set-rate-parent: 120 type: boolean 121 description: 122 clk_set_rate is propagated to parent | 123 124 ti,latch-bit: 125 $ref: /schemas/types.yaml#/definitions/uint32 126 description: 127 latch the divider value to HW, only needed if the register 128 compatible access requires this. As an example dra76x DPLL_GMAC 129 H14 divider implements such behavior. 130 131dependentSchemas: 132 ti,dividers: 133 properties: 134 ti,min-div: false 135 ti,max-div: false 136 ti,index-power-of-two: false 137 ti,index-starts-at-one: false 138 139required: 140 - compatible 141 - "#clock-cells" 142 - clocks 143 - reg 144 145unevaluatedProperties: false 146 147examples: 148 - | 149 bus { 150 #address-cells = <1>; 151 #size-cells = <0>; 152 153 clock-controller@190 { 154 #clock-cells = <0>; 155 compatible = "ti,divider-clock"; 156 clocks = <&dpll_usb_ck>; 157 ti,max-div = <127>; 158 reg = <0x190>; 159 ti,index-starts-at-one; 160 }; 161 162 clock-controller@528 { 163 #clock-cells = <0>; 164 compatible = "ti,divider-clock"; 165 clocks = <&abe_clk>; 166 ti,bit-shift = <24>; 167 reg = <0x528>; 168 ti,max-div = <2>; 169 }; 170 171 clock-controller@a40 { 172 #clock-cells = <0>; 173 compatible = "ti,composite-divider-clock"; 174 clocks = <&corex2_fck>; 175 ti,bit-shift = <8>; 176 reg = <0x0a40>; 177 ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>; 178 }; 179 }; 180