1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
76 	{ "ti,mux-clock",		TI_MUX_CLOCK },
77 	{ "ti,composite-mux-clock",	TI_COMPOSITE_MUX_CLOCK },
87 	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)  in ti_mux_probe()
99 	sc->clkdom = clkdom_create(sc->sc_dev);  in register_clk()
100 	if (sc->clkdom == NULL) {  in register_clk()
101 		DPRINTF(sc->sc_dev, "Failed to create clkdom\n");  in register_clk()
105 	err = clknode_mux_register(sc->clkdom, &sc->mux_def);  in register_clk()
107 		DPRINTF(sc->sc_dev, "clknode_mux_register failed %x\n", err);  in register_clk()
111 	err = clkdom_finit(sc->clkdom);  in register_clk()
113 		DPRINTF(sc->sc_dev, "Clk domain finit fails %x.\n", err);  in register_clk()
129 	sc->sc_dev = dev;  in ti_mux_attach()
134 	sc->mux_def.offset = value;  in ti_mux_attach()
136 	if (OF_hasprop(node, "ti,bit-shift")) {  in ti_mux_attach()
137 		OF_getencprop(node, "ti,bit-shift", &value, sizeof(value));  in ti_mux_attach()
138 		sc->mux_def.shift = value;  in ti_mux_attach()
139 		DPRINTF(sc->sc_dev, "ti,bit-shift => shift %x\n", sc->mux_def.shift);  in ti_mux_attach()
141 	if (OF_hasprop(node, "ti,index-starts-at-one")) {  in ti_mux_attach()
143 		/*sc->mux_def.mux_flags =  ... */  in ti_mux_attach()
144 		device_printf(sc->sc_dev, "ti,index-starts-at-one - Not implemented\n");  in ti_mux_attach()
147 	if (OF_hasprop(node, "ti,set-rate-parent"))  in ti_mux_attach()
148 		device_printf(sc->sc_dev, "ti,set-rate-parent - Not implemented\n");  in ti_mux_attach()
149 	if (OF_hasprop(node, "ti,latch-bit"))  in ti_mux_attach()
150 		device_printf(sc->sc_dev, "ti,latch-bit - Not implemented\n");  in ti_mux_attach()
152 	read_clock_cells(sc->sc_dev, &sc->clock_cell);  in ti_mux_attach()
154 	create_clkdef(sc->sc_dev, &sc->clock_cell, &sc->mux_def.clkdef);  in ti_mux_attach()
157 	if (sc->mux_def.mux_flags)  in ti_mux_attach()
158 		sc->mux_def.width = fls(sc->clock_cell.num_real_clocks-1);  in ti_mux_attach()
160 		sc->mux_def.width = fls(sc->clock_cell.num_real_clocks);  in ti_mux_attach()
162 	DPRINTF(sc->sc_dev, "sc->clock_cell.num_real_clocks %x def.width %x\n",  in ti_mux_attach()
163 		sc->clock_cell.num_real_clocks, sc->mux_def.width);  in ti_mux_attach()
165 	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->mux_def.clkdef);  in ti_mux_attach()
169 		DPRINTF(sc->sc_dev, "find_parent_clock_names failed\n");  in ti_mux_attach()
170 		bus_attach_children(sc->dev);  in ti_mux_attach()
178 		DPRINTF(sc->sc_dev, "register_clk failed\n");  in ti_mux_attach()
179 		bus_attach_children(sc->dev);  in ti_mux_attach()
183 	sc->attach_done = true;  in ti_mux_attach()
185 	free_clkdef(&sc->mux_def.clkdef);  in ti_mux_attach()
187 	bus_attach_children(sc->dev);  in ti_mux_attach()
199 	if (sc->attach_done) {  in ti_mux_new_pass()
203 	err = find_parent_clock_names(sc->sc_dev, &sc->clock_cell, &sc->mux_def.clkdef);  in ti_mux_new_pass()
206 		DPRINTF(sc->sc_dev, "ti_mux_new_pass find_parent_clock_names failed\n");  in ti_mux_new_pass()
213 		DPRINTF(sc->sc_dev, "ti_mux_new_pass register_clk failed\n");  in ti_mux_new_pass()
217 	sc->attach_done = true;  in ti_mux_new_pass()
219 	free_clkdef(&sc->mux_def.clkdef);  in ti_mux_new_pass()