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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dingenic,nemc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ingenic,nemc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs NAND / External Memory Controller (NEMC)
10 - Paul Cercueil <paul@crapouillou.net>
14 pattern: "^memory-controller@[0-9a-f]+$"
18 - enum:
19 - ingenic,jz4740-nemc
20 - ingenic,jz4780-nemc
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/linux/drivers/memory/
H A Djz4780-nemc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * JZ4780 NAND/external memory controller (NEMC)
6 * Author: Alex Smith <alex@alex-smith.me.uk>
20 #include <linux/jz4780-nemc.h>
22 #define NEMC_SMCRn(n) (0x14 + (((n) - 1) * 4))
42 #define NEMC_NFCSR_NFEn(n) BIT(((n) - 1) << 1)
43 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
44 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
61 * jz4780_nemc_num_banks() - count the number of banks referenced by a device
62 * @dev: device to count banks for, must be a child of the NEMC.
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
42 Used to configure the EBI (external bus interface) when the device-
68 bool "Baikal-T1 CM2 L2-RAM Cache Control Block"
72 Baikal-T1 CPU is based on the MIPS P5600 Warrior IP-core. The CPU
73 resides Coherency Manager v2 with embedded 1MB L2-cache. It's
75 tags and way-select latencies of RAM access. This driver provides a
76 dt properties-based and sysfs interface for it.
85 is intended to provide a glue-less interface to a variety of
99 functions of the driver includes re-configuring AC timing
135 the EMIF PM code must run from on-chip SRAM late in the suspend
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
6 obj-$(CONFIG_DDR) += jedec_ddr_data.o
8 obj-$(CONFIG_OF) += of_memory.o
10 obj-$(CONFIG_ARM_PL172_MPMC) += pl172.o
11 obj-$(CONFIG_ATMEL_EBI) += atmel-ebi.o
12 obj-$(CONFIG_BRCMSTB_DPFE) += brcmstb_dpfe.o
13 obj-$(CONFIG_BRCMSTB_MEMC) += brcmstb_memc.o
14 obj-$(CONFIG_BT1_L2_CTL) += bt1-l2-ctl.o
15 obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
16 obj-$(CONFIG_TI_EMIF) += emif.o
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/linux/Documentation/devicetree/bindings/mtd/
H A Dingenic,nand.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: nand-controller.yaml#
14 - $ref: /schemas/memory-controllers/ingenic,nemc-peripherals.yaml#
19 - ingenic,jz4740-nand
20 - ingenic,jz4725b-nand
21 - ingenic,jz4780-nand
25 - description: Bank number, offset and size of first attached NAND chip
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/linux/arch/mips/boot/dts/ingenic/
H A Dci20.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "jz4780.dtsi"
5 #include <dt-bindings/clock/ingenic,tcu.h>
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/regulator/active-semi,8865-regulator.h>
12 compatible = "img,ci20", "ingenic,jz4780";
22 stdout-path = &uart4;
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H A Djz4780.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
3 #include <dt-bindings/clock/ingenic,tcu.h>
4 #include <dt-bindings/dma/jz4780-dma.h>
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "ingenic,jz4780";
12 #address-cells = <1>;
13 #size-cells = <0>;
17 compatible = "ingenic,xburst-fpu1.0-mxu1.1";
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/linux/drivers/mtd/nand/raw/ingenic/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 tristate "JZ4780 NAND controller"
7 Enables support for NAND Flash connected to the NEMC on JZ4780 SoC
19 Enable this driver to support the Reed-Solomon error-correction
23 will be called jz4740-ecc.
29 Enable this driver to support the BCH error-correction hardware
33 will be called jz4725b-bch.
36 tristate "Hardware BCH support for JZ4780 SoC"
39 Enable this driver to support the BCH error-correction hardware
40 present on the JZ4780 SoC from Ingenic.
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H A Dingenic_nand_drv.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc()
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free()
93 return -ERANGE; in qi_lb60_ooblayout_free()
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/linux/include/linux/
H A Djz4780-nemc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * JZ4780 NAND/external memory controller (NEMC)
6 * Author: Alex Smith <alex@alex-smith.me.uk>
17 * Number of NEMC banks. Note that there are actually 6, but they are numbered
23 * enum jz4780_nemc_bank_type - device types which can be connected to a bank
/linux/drivers/clk/ingenic/
H A Djz4780-cgu.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 SoC CGU driver
5 * Copyright (c) 2013-2015 Imagination Technologies
10 #include <linux/clk-provider.h>
16 #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
111 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_recalc_rate()
170 return -EINVAL; in jz4780_otg_phy_set_rate()
173 spin_lock_irqsave(&cgu->lock, flags); in jz4780_otg_phy_set_rate()
175 usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
178 writel(usbpcr1, cgu->base + CGU_REG_USBPCR1); in jz4780_otg_phy_set_rate()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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