1c942fddfSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
229136ad5SPaul Burton /*
329136ad5SPaul Burton * Ingenic JZ4780 SoC CGU driver
429136ad5SPaul Burton *
529136ad5SPaul Burton * Copyright (c) 2013-2015 Imagination Technologies
6fb615d61SPaul Burton * Author: Paul Burton <paul.burton@mips.com>
7dcd062a8S周琰杰 (Zhou Yanjie) * Copyright (c) 2020 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
829136ad5SPaul Burton */
929136ad5SPaul Burton
1029136ad5SPaul Burton #include <linux/clk-provider.h>
1129136ad5SPaul Burton #include <linux/delay.h>
1262e59c4eSStephen Boyd #include <linux/io.h>
136673db4fS周琰杰 (Zhou Yanjie) #include <linux/iopoll.h>
1429136ad5SPaul Burton #include <linux/of.h>
156673db4fS周琰杰 (Zhou Yanjie)
16c4a11bf4SPaul Cercueil #include <dt-bindings/clock/ingenic,jz4780-cgu.h>
179d9cc58aS周琰杰 (Zhou Yanjie)
1829136ad5SPaul Burton #include "cgu.h"
192ee93e3cSPaul Cercueil #include "pm.h"
2029136ad5SPaul Burton
2129136ad5SPaul Burton /* CGU register offsets */
2229136ad5SPaul Burton #define CGU_REG_CLOCKCONTROL 0x00
236673db4fS周琰杰 (Zhou Yanjie) #define CGU_REG_LCR 0x04
2429136ad5SPaul Burton #define CGU_REG_APLL 0x10
2529136ad5SPaul Burton #define CGU_REG_MPLL 0x14
2629136ad5SPaul Burton #define CGU_REG_EPLL 0x18
2729136ad5SPaul Burton #define CGU_REG_VPLL 0x1c
2829136ad5SPaul Burton #define CGU_REG_CLKGR0 0x20
2929136ad5SPaul Burton #define CGU_REG_OPCR 0x24
3029136ad5SPaul Burton #define CGU_REG_CLKGR1 0x28
3129136ad5SPaul Burton #define CGU_REG_DDRCDR 0x2c
3229136ad5SPaul Burton #define CGU_REG_VPUCDR 0x30
3329136ad5SPaul Burton #define CGU_REG_USBPCR 0x3c
3429136ad5SPaul Burton #define CGU_REG_USBRDT 0x40
3529136ad5SPaul Burton #define CGU_REG_USBVBFIL 0x44
3629136ad5SPaul Burton #define CGU_REG_USBPCR1 0x48
3729136ad5SPaul Burton #define CGU_REG_LP0CDR 0x54
3829136ad5SPaul Burton #define CGU_REG_I2SCDR 0x60
3929136ad5SPaul Burton #define CGU_REG_LP1CDR 0x64
4029136ad5SPaul Burton #define CGU_REG_MSC0CDR 0x68
4129136ad5SPaul Burton #define CGU_REG_UHCCDR 0x6c
4229136ad5SPaul Burton #define CGU_REG_SSICDR 0x74
4329136ad5SPaul Burton #define CGU_REG_CIMCDR 0x7c
4429136ad5SPaul Burton #define CGU_REG_PCMCDR 0x84
4529136ad5SPaul Burton #define CGU_REG_GPUCDR 0x88
4629136ad5SPaul Burton #define CGU_REG_HDMICDR 0x8c
4729136ad5SPaul Burton #define CGU_REG_MSC1CDR 0xa4
4829136ad5SPaul Burton #define CGU_REG_MSC2CDR 0xa8
4929136ad5SPaul Burton #define CGU_REG_BCHCDR 0xac
5029136ad5SPaul Burton #define CGU_REG_CLOCKSTATUS 0xd4
5129136ad5SPaul Burton
5229136ad5SPaul Burton /* bits within the OPCR register */
536673db4fS周琰杰 (Zhou Yanjie) #define OPCR_SPENDN0 BIT(7)
546673db4fS周琰杰 (Zhou Yanjie) #define OPCR_SPENDN1 BIT(6)
5529136ad5SPaul Burton
5629136ad5SPaul Burton /* bits within the USBPCR register */
5729136ad5SPaul Burton #define USBPCR_USB_MODE BIT(31)
5829136ad5SPaul Burton #define USBPCR_IDPULLUP_MASK (0x3 << 28)
5929136ad5SPaul Burton #define USBPCR_COMMONONN BIT(25)
6029136ad5SPaul Burton #define USBPCR_VBUSVLDEXT BIT(24)
6129136ad5SPaul Burton #define USBPCR_VBUSVLDEXTSEL BIT(23)
6229136ad5SPaul Burton #define USBPCR_POR BIT(22)
63dcd062a8S周琰杰 (Zhou Yanjie) #define USBPCR_SIDDQ BIT(21)
6429136ad5SPaul Burton #define USBPCR_OTG_DISABLE BIT(20)
6529136ad5SPaul Burton #define USBPCR_COMPDISTUNE_MASK (0x7 << 17)
6629136ad5SPaul Burton #define USBPCR_OTGTUNE_MASK (0x7 << 14)
6729136ad5SPaul Burton #define USBPCR_SQRXTUNE_MASK (0x7 << 11)
6829136ad5SPaul Burton #define USBPCR_TXFSLSTUNE_MASK (0xf << 7)
6929136ad5SPaul Burton #define USBPCR_TXPREEMPHTUNE BIT(6)
7029136ad5SPaul Burton #define USBPCR_TXHSXVTUNE_MASK (0x3 << 4)
7129136ad5SPaul Burton #define USBPCR_TXVREFTUNE_MASK 0xf
7229136ad5SPaul Burton
7329136ad5SPaul Burton /* bits within the USBPCR1 register */
7429136ad5SPaul Burton #define USBPCR1_REFCLKSEL_SHIFT 26
7529136ad5SPaul Burton #define USBPCR1_REFCLKSEL_MASK (0x3 << USBPCR1_REFCLKSEL_SHIFT)
7629136ad5SPaul Burton #define USBPCR1_REFCLKSEL_CORE (0x2 << USBPCR1_REFCLKSEL_SHIFT)
7729136ad5SPaul Burton #define USBPCR1_REFCLKDIV_SHIFT 24
7829136ad5SPaul Burton #define USBPCR1_REFCLKDIV_MASK (0x3 << USBPCR1_REFCLKDIV_SHIFT)
7929136ad5SPaul Burton #define USBPCR1_REFCLKDIV_19_2 (0x3 << USBPCR1_REFCLKDIV_SHIFT)
8029136ad5SPaul Burton #define USBPCR1_REFCLKDIV_48 (0x2 << USBPCR1_REFCLKDIV_SHIFT)
8129136ad5SPaul Burton #define USBPCR1_REFCLKDIV_24 (0x1 << USBPCR1_REFCLKDIV_SHIFT)
8229136ad5SPaul Burton #define USBPCR1_REFCLKDIV_12 (0x0 << USBPCR1_REFCLKDIV_SHIFT)
8329136ad5SPaul Burton #define USBPCR1_USB_SEL BIT(28)
8429136ad5SPaul Burton #define USBPCR1_WORD_IF0 BIT(19)
8529136ad5SPaul Burton #define USBPCR1_WORD_IF1 BIT(18)
8629136ad5SPaul Burton
8729136ad5SPaul Burton /* bits within the USBRDT register */
8829136ad5SPaul Burton #define USBRDT_VBFIL_LD_EN BIT(25)
8929136ad5SPaul Burton #define USBRDT_USBRDT_MASK 0x7fffff
9029136ad5SPaul Burton
9129136ad5SPaul Burton /* bits within the USBVBFIL register */
9229136ad5SPaul Burton #define USBVBFIL_IDDIGFIL_SHIFT 16
9329136ad5SPaul Burton #define USBVBFIL_IDDIGFIL_MASK (0xffff << USBVBFIL_IDDIGFIL_SHIFT)
9429136ad5SPaul Burton #define USBVBFIL_USBVBFIL_MASK (0xffff)
9529136ad5SPaul Burton
966673db4fS周琰杰 (Zhou Yanjie) /* bits within the LCR register */
976673db4fS周琰杰 (Zhou Yanjie) #define LCR_PD_SCPU BIT(31)
986673db4fS周琰杰 (Zhou Yanjie) #define LCR_SCPUS BIT(27)
996673db4fS周琰杰 (Zhou Yanjie)
1006673db4fS周琰杰 (Zhou Yanjie) /* bits within the CLKGR1 register */
1016673db4fS周琰杰 (Zhou Yanjie) #define CLKGR1_CORE1 BIT(15)
1026673db4fS周琰杰 (Zhou Yanjie)
10329136ad5SPaul Burton static struct ingenic_cgu *cgu;
10429136ad5SPaul Burton
jz4780_otg_phy_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)10529136ad5SPaul Burton static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
10629136ad5SPaul Burton unsigned long parent_rate)
10729136ad5SPaul Burton {
10829136ad5SPaul Burton u32 usbpcr1;
10929136ad5SPaul Burton unsigned refclk_div;
11029136ad5SPaul Burton
11129136ad5SPaul Burton usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
11229136ad5SPaul Burton refclk_div = usbpcr1 & USBPCR1_REFCLKDIV_MASK;
11329136ad5SPaul Burton
11429136ad5SPaul Burton switch (refclk_div) {
11529136ad5SPaul Burton case USBPCR1_REFCLKDIV_12:
11629136ad5SPaul Burton return 12000000;
11729136ad5SPaul Burton
11829136ad5SPaul Burton case USBPCR1_REFCLKDIV_24:
11929136ad5SPaul Burton return 24000000;
12029136ad5SPaul Burton
12129136ad5SPaul Burton case USBPCR1_REFCLKDIV_48:
12229136ad5SPaul Burton return 48000000;
12329136ad5SPaul Burton
12429136ad5SPaul Burton case USBPCR1_REFCLKDIV_19_2:
12529136ad5SPaul Burton return 19200000;
12629136ad5SPaul Burton }
12729136ad5SPaul Burton
12829136ad5SPaul Burton return parent_rate;
12929136ad5SPaul Burton }
13029136ad5SPaul Burton
jz4780_otg_phy_round_rate(struct clk_hw * hw,unsigned long req_rate,unsigned long * parent_rate)13129136ad5SPaul Burton static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
13229136ad5SPaul Burton unsigned long *parent_rate)
13329136ad5SPaul Burton {
13429136ad5SPaul Burton if (req_rate < 15600000)
13529136ad5SPaul Burton return 12000000;
13629136ad5SPaul Burton
13729136ad5SPaul Burton if (req_rate < 21600000)
13829136ad5SPaul Burton return 19200000;
13929136ad5SPaul Burton
14029136ad5SPaul Burton if (req_rate < 36000000)
14129136ad5SPaul Burton return 24000000;
14229136ad5SPaul Burton
14329136ad5SPaul Burton return 48000000;
14429136ad5SPaul Burton }
14529136ad5SPaul Burton
jz4780_otg_phy_set_rate(struct clk_hw * hw,unsigned long req_rate,unsigned long parent_rate)14629136ad5SPaul Burton static int jz4780_otg_phy_set_rate(struct clk_hw *hw, unsigned long req_rate,
14729136ad5SPaul Burton unsigned long parent_rate)
14829136ad5SPaul Burton {
14929136ad5SPaul Burton unsigned long flags;
15029136ad5SPaul Burton u32 usbpcr1, div_bits;
15129136ad5SPaul Burton
15229136ad5SPaul Burton switch (req_rate) {
15329136ad5SPaul Burton case 12000000:
15429136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_12;
15529136ad5SPaul Burton break;
15629136ad5SPaul Burton
15729136ad5SPaul Burton case 19200000:
15829136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_19_2;
15929136ad5SPaul Burton break;
16029136ad5SPaul Burton
16129136ad5SPaul Burton case 24000000:
16229136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_24;
16329136ad5SPaul Burton break;
16429136ad5SPaul Burton
16529136ad5SPaul Burton case 48000000:
16629136ad5SPaul Burton div_bits = USBPCR1_REFCLKDIV_48;
16729136ad5SPaul Burton break;
16829136ad5SPaul Burton
16929136ad5SPaul Burton default:
17029136ad5SPaul Burton return -EINVAL;
17129136ad5SPaul Burton }
17229136ad5SPaul Burton
17329136ad5SPaul Burton spin_lock_irqsave(&cgu->lock, flags);
17429136ad5SPaul Burton
17529136ad5SPaul Burton usbpcr1 = readl(cgu->base + CGU_REG_USBPCR1);
17629136ad5SPaul Burton usbpcr1 &= ~USBPCR1_REFCLKDIV_MASK;
17729136ad5SPaul Burton usbpcr1 |= div_bits;
17829136ad5SPaul Burton writel(usbpcr1, cgu->base + CGU_REG_USBPCR1);
17929136ad5SPaul Burton
18029136ad5SPaul Burton spin_unlock_irqrestore(&cgu->lock, flags);
18129136ad5SPaul Burton return 0;
18229136ad5SPaul Burton }
18329136ad5SPaul Burton
jz4780_otg_phy_enable(struct clk_hw * hw)184dcd062a8S周琰杰 (Zhou Yanjie) static int jz4780_otg_phy_enable(struct clk_hw *hw)
185dcd062a8S周琰杰 (Zhou Yanjie) {
186dcd062a8S周琰杰 (Zhou Yanjie) void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
187dcd062a8S周琰杰 (Zhou Yanjie) void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
18829136ad5SPaul Burton
189dcd062a8S周琰杰 (Zhou Yanjie) writel(readl(reg_opcr) | OPCR_SPENDN0, reg_opcr);
190dcd062a8S周琰杰 (Zhou Yanjie) writel(readl(reg_usbpcr) & ~USBPCR_OTG_DISABLE & ~USBPCR_SIDDQ, reg_usbpcr);
191dcd062a8S周琰杰 (Zhou Yanjie) return 0;
192dcd062a8S周琰杰 (Zhou Yanjie) }
193dcd062a8S周琰杰 (Zhou Yanjie)
jz4780_otg_phy_disable(struct clk_hw * hw)194dcd062a8S周琰杰 (Zhou Yanjie) static void jz4780_otg_phy_disable(struct clk_hw *hw)
195dcd062a8S周琰杰 (Zhou Yanjie) {
196dcd062a8S周琰杰 (Zhou Yanjie) void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
197dcd062a8S周琰杰 (Zhou Yanjie) void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
198dcd062a8S周琰杰 (Zhou Yanjie)
199dcd062a8S周琰杰 (Zhou Yanjie) writel(readl(reg_opcr) & ~OPCR_SPENDN0, reg_opcr);
200dcd062a8S周琰杰 (Zhou Yanjie) writel(readl(reg_usbpcr) | USBPCR_OTG_DISABLE | USBPCR_SIDDQ, reg_usbpcr);
201dcd062a8S周琰杰 (Zhou Yanjie) }
202dcd062a8S周琰杰 (Zhou Yanjie)
jz4780_otg_phy_is_enabled(struct clk_hw * hw)203dcd062a8S周琰杰 (Zhou Yanjie) static int jz4780_otg_phy_is_enabled(struct clk_hw *hw)
204dcd062a8S周琰杰 (Zhou Yanjie) {
205dcd062a8S周琰杰 (Zhou Yanjie) void __iomem *reg_opcr = cgu->base + CGU_REG_OPCR;
206dcd062a8S周琰杰 (Zhou Yanjie) void __iomem *reg_usbpcr = cgu->base + CGU_REG_USBPCR;
207dcd062a8S周琰杰 (Zhou Yanjie)
208dcd062a8S周琰杰 (Zhou Yanjie) return (readl(reg_opcr) & OPCR_SPENDN0) &&
209dcd062a8S周琰杰 (Zhou Yanjie) !(readl(reg_usbpcr) & USBPCR_SIDDQ) &&
210dcd062a8S周琰杰 (Zhou Yanjie) !(readl(reg_usbpcr) & USBPCR_OTG_DISABLE);
211dcd062a8S周琰杰 (Zhou Yanjie) }
212dcd062a8S周琰杰 (Zhou Yanjie)
213dcd062a8S周琰杰 (Zhou Yanjie) static const struct clk_ops jz4780_otg_phy_ops = {
21429136ad5SPaul Burton .recalc_rate = jz4780_otg_phy_recalc_rate,
21529136ad5SPaul Burton .round_rate = jz4780_otg_phy_round_rate,
21629136ad5SPaul Burton .set_rate = jz4780_otg_phy_set_rate,
217dcd062a8S周琰杰 (Zhou Yanjie)
218dcd062a8S周琰杰 (Zhou Yanjie) .enable = jz4780_otg_phy_enable,
219dcd062a8S周琰杰 (Zhou Yanjie) .disable = jz4780_otg_phy_disable,
220dcd062a8S周琰杰 (Zhou Yanjie) .is_enabled = jz4780_otg_phy_is_enabled,
22129136ad5SPaul Burton };
22229136ad5SPaul Burton
jz4780_core1_enable(struct clk_hw * hw)2236673db4fS周琰杰 (Zhou Yanjie) static int jz4780_core1_enable(struct clk_hw *hw)
2246673db4fS周琰杰 (Zhou Yanjie) {
2256673db4fS周琰杰 (Zhou Yanjie) struct ingenic_clk *ingenic_clk = to_ingenic_clk(hw);
2266673db4fS周琰杰 (Zhou Yanjie) struct ingenic_cgu *cgu = ingenic_clk->cgu;
2276673db4fS周琰杰 (Zhou Yanjie) const unsigned int timeout = 5000;
2286673db4fS周琰杰 (Zhou Yanjie) unsigned long flags;
2296673db4fS周琰杰 (Zhou Yanjie) int retval;
2306673db4fS周琰杰 (Zhou Yanjie) u32 lcr, clkgr1;
2316673db4fS周琰杰 (Zhou Yanjie)
2326673db4fS周琰杰 (Zhou Yanjie) spin_lock_irqsave(&cgu->lock, flags);
2336673db4fS周琰杰 (Zhou Yanjie)
2346673db4fS周琰杰 (Zhou Yanjie) lcr = readl(cgu->base + CGU_REG_LCR);
2356673db4fS周琰杰 (Zhou Yanjie) lcr &= ~LCR_PD_SCPU;
2366673db4fS周琰杰 (Zhou Yanjie) writel(lcr, cgu->base + CGU_REG_LCR);
2376673db4fS周琰杰 (Zhou Yanjie)
2386673db4fS周琰杰 (Zhou Yanjie) clkgr1 = readl(cgu->base + CGU_REG_CLKGR1);
2396673db4fS周琰杰 (Zhou Yanjie) clkgr1 &= ~CLKGR1_CORE1;
2406673db4fS周琰杰 (Zhou Yanjie) writel(clkgr1, cgu->base + CGU_REG_CLKGR1);
2416673db4fS周琰杰 (Zhou Yanjie)
2426673db4fS周琰杰 (Zhou Yanjie) spin_unlock_irqrestore(&cgu->lock, flags);
2436673db4fS周琰杰 (Zhou Yanjie)
2446673db4fS周琰杰 (Zhou Yanjie) /* wait for the CPU to be powered up */
2456673db4fS周琰杰 (Zhou Yanjie) retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr,
2466673db4fS周琰杰 (Zhou Yanjie) !(lcr & LCR_SCPUS), 10, timeout);
2476673db4fS周琰杰 (Zhou Yanjie) if (retval == -ETIMEDOUT) {
2486673db4fS周琰杰 (Zhou Yanjie) pr_err("%s: Wait for power up core1 timeout\n", __func__);
2496673db4fS周琰杰 (Zhou Yanjie) return retval;
2506673db4fS周琰杰 (Zhou Yanjie) }
2516673db4fS周琰杰 (Zhou Yanjie)
2526673db4fS周琰杰 (Zhou Yanjie) return 0;
2536673db4fS周琰杰 (Zhou Yanjie) }
2546673db4fS周琰杰 (Zhou Yanjie)
2556673db4fS周琰杰 (Zhou Yanjie) static const struct clk_ops jz4780_core1_ops = {
2566673db4fS周琰杰 (Zhou Yanjie) .enable = jz4780_core1_enable,
2576673db4fS周琰杰 (Zhou Yanjie) };
2586673db4fS周琰杰 (Zhou Yanjie)
25929136ad5SPaul Burton static const s8 pll_od_encoding[16] = {
26029136ad5SPaul Burton 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7,
26129136ad5SPaul Burton 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf,
26229136ad5SPaul Burton };
26329136ad5SPaul Burton
26429136ad5SPaul Burton static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
26529136ad5SPaul Burton
26629136ad5SPaul Burton /* External clocks */
26729136ad5SPaul Burton
26829136ad5SPaul Burton [JZ4780_CLK_EXCLK] = { "ext", CGU_CLK_EXT },
26929136ad5SPaul Burton [JZ4780_CLK_RTCLK] = { "rtc", CGU_CLK_EXT },
27029136ad5SPaul Burton
27129136ad5SPaul Burton /* PLLs */
27229136ad5SPaul Burton
27329136ad5SPaul Burton #define DEF_PLL(name) { \
27429136ad5SPaul Burton .reg = CGU_REG_ ## name, \
2759d9cc58aS周琰杰 (Zhou Yanjie) .rate_multiplier = 1, \
27629136ad5SPaul Burton .m_shift = 19, \
27729136ad5SPaul Burton .m_bits = 13, \
27829136ad5SPaul Burton .m_offset = 1, \
27929136ad5SPaul Burton .n_shift = 13, \
28029136ad5SPaul Burton .n_bits = 6, \
28129136ad5SPaul Burton .n_offset = 1, \
28229136ad5SPaul Burton .od_shift = 9, \
28329136ad5SPaul Burton .od_bits = 4, \
28429136ad5SPaul Burton .od_max = 16, \
28529136ad5SPaul Burton .od_encoding = pll_od_encoding, \
28629136ad5SPaul Burton .stable_bit = 6, \
2879d9cc58aS周琰杰 (Zhou Yanjie) .bypass_reg = CGU_REG_ ## name, \
28829136ad5SPaul Burton .bypass_bit = 1, \
28929136ad5SPaul Burton .enable_bit = 0, \
29029136ad5SPaul Burton }
29129136ad5SPaul Burton
29229136ad5SPaul Burton [JZ4780_CLK_APLL] = {
29329136ad5SPaul Burton "apll", CGU_CLK_PLL,
29429136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
29529136ad5SPaul Burton .pll = DEF_PLL(APLL),
29629136ad5SPaul Burton },
29729136ad5SPaul Burton
29829136ad5SPaul Burton [JZ4780_CLK_MPLL] = {
29929136ad5SPaul Burton "mpll", CGU_CLK_PLL,
30029136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
30129136ad5SPaul Burton .pll = DEF_PLL(MPLL),
30229136ad5SPaul Burton },
30329136ad5SPaul Burton
30429136ad5SPaul Burton [JZ4780_CLK_EPLL] = {
30529136ad5SPaul Burton "epll", CGU_CLK_PLL,
30629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
30729136ad5SPaul Burton .pll = DEF_PLL(EPLL),
30829136ad5SPaul Burton },
30929136ad5SPaul Burton
31029136ad5SPaul Burton [JZ4780_CLK_VPLL] = {
31129136ad5SPaul Burton "vpll", CGU_CLK_PLL,
31229136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
31329136ad5SPaul Burton .pll = DEF_PLL(VPLL),
31429136ad5SPaul Burton },
31529136ad5SPaul Burton
31629136ad5SPaul Burton #undef DEF_PLL
31729136ad5SPaul Burton
31829136ad5SPaul Burton /* Custom (SoC-specific) OTG PHY */
31929136ad5SPaul Burton
32029136ad5SPaul Burton [JZ4780_CLK_OTGPHY] = {
32129136ad5SPaul Burton "otg_phy", CGU_CLK_CUSTOM,
32229136ad5SPaul Burton .parents = { -1, -1, JZ4780_CLK_EXCLK, -1 },
32329136ad5SPaul Burton .custom = { &jz4780_otg_phy_ops },
32429136ad5SPaul Burton },
32529136ad5SPaul Burton
32629136ad5SPaul Burton /* Muxes & dividers */
32729136ad5SPaul Burton
32829136ad5SPaul Burton [JZ4780_CLK_SCLKA] = {
32929136ad5SPaul Burton "sclk_a", CGU_CLK_MUX,
33029136ad5SPaul Burton .parents = { -1, JZ4780_CLK_APLL, JZ4780_CLK_EXCLK,
33129136ad5SPaul Burton JZ4780_CLK_RTCLK },
33229136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 30, 2 },
33329136ad5SPaul Burton },
33429136ad5SPaul Burton
33529136ad5SPaul Burton [JZ4780_CLK_CPUMUX] = {
33629136ad5SPaul Burton "cpumux", CGU_CLK_MUX,
33729136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
33829136ad5SPaul Burton JZ4780_CLK_EPLL },
33929136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 28, 2 },
34029136ad5SPaul Burton },
34129136ad5SPaul Burton
34229136ad5SPaul Burton [JZ4780_CLK_CPU] = {
34329136ad5SPaul Burton "cpu", CGU_CLK_DIV,
344*ca54d06fSAidan MacDonald /*
345*ca54d06fSAidan MacDonald * Disabling the CPU clock or any parent clocks will hang the
346*ca54d06fSAidan MacDonald * system; mark it critical.
347*ca54d06fSAidan MacDonald */
348*ca54d06fSAidan MacDonald .flags = CLK_IS_CRITICAL,
34929136ad5SPaul Burton .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
3504afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
35129136ad5SPaul Burton },
35229136ad5SPaul Burton
35329136ad5SPaul Burton [JZ4780_CLK_L2CACHE] = {
35429136ad5SPaul Burton "l2cache", CGU_CLK_DIV,
355*ca54d06fSAidan MacDonald /*
356*ca54d06fSAidan MacDonald * The L2 cache clock is critical if caches are enabled and
357*ca54d06fSAidan MacDonald * disabling it or any parent clocks will hang the system.
358*ca54d06fSAidan MacDonald */
359*ca54d06fSAidan MacDonald .flags = CLK_IS_CRITICAL,
36029136ad5SPaul Burton .parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
3614afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
36229136ad5SPaul Burton },
36329136ad5SPaul Burton
36429136ad5SPaul Burton [JZ4780_CLK_AHB0] = {
36529136ad5SPaul Burton "ahb0", CGU_CLK_MUX | CGU_CLK_DIV,
36629136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
36729136ad5SPaul Burton JZ4780_CLK_EPLL },
36829136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
3694afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
37029136ad5SPaul Burton },
37129136ad5SPaul Burton
37229136ad5SPaul Burton [JZ4780_CLK_AHB2PMUX] = {
37329136ad5SPaul Burton "ahb2_apb_mux", CGU_CLK_MUX,
37429136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
37529136ad5SPaul Burton JZ4780_CLK_RTCLK },
37629136ad5SPaul Burton .mux = { CGU_REG_CLOCKCONTROL, 24, 2 },
37729136ad5SPaul Burton },
37829136ad5SPaul Burton
37929136ad5SPaul Burton [JZ4780_CLK_AHB2] = {
38029136ad5SPaul Burton "ahb2", CGU_CLK_DIV,
38129136ad5SPaul Burton .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
3824afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
38329136ad5SPaul Burton },
38429136ad5SPaul Burton
38529136ad5SPaul Burton [JZ4780_CLK_PCLK] = {
38629136ad5SPaul Burton "pclk", CGU_CLK_DIV,
38729136ad5SPaul Burton .parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
3884afe2d1aSHarvey Hunt .div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
38929136ad5SPaul Burton },
39029136ad5SPaul Burton
39129136ad5SPaul Burton [JZ4780_CLK_DDR] = {
39229136ad5SPaul Burton "ddr", CGU_CLK_MUX | CGU_CLK_DIV,
393*ca54d06fSAidan MacDonald /*
394*ca54d06fSAidan MacDonald * Disabling DDR clock or its parents will render DRAM
395*ca54d06fSAidan MacDonald * inaccessible; mark it critical.
396*ca54d06fSAidan MacDonald */
397*ca54d06fSAidan MacDonald .flags = CLK_IS_CRITICAL,
39829136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
39929136ad5SPaul Burton .mux = { CGU_REG_DDRCDR, 30, 2 },
4004afe2d1aSHarvey Hunt .div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
40129136ad5SPaul Burton },
40229136ad5SPaul Burton
40329136ad5SPaul Burton [JZ4780_CLK_VPU] = {
40429136ad5SPaul Burton "vpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
40529136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
40629136ad5SPaul Burton JZ4780_CLK_EPLL, -1 },
40729136ad5SPaul Burton .mux = { CGU_REG_VPUCDR, 30, 2 },
4084afe2d1aSHarvey Hunt .div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 },
40929136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 2 },
41029136ad5SPaul Burton },
41129136ad5SPaul Burton
41229136ad5SPaul Burton [JZ4780_CLK_I2SPLL] = {
41329136ad5SPaul Burton "i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
41429136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
41529136ad5SPaul Burton .mux = { CGU_REG_I2SCDR, 30, 1 },
4164afe2d1aSHarvey Hunt .div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 },
41729136ad5SPaul Burton },
41829136ad5SPaul Burton
41929136ad5SPaul Burton [JZ4780_CLK_I2S] = {
42029136ad5SPaul Burton "i2s", CGU_CLK_MUX,
42129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_I2SPLL, -1, -1 },
42229136ad5SPaul Burton .mux = { CGU_REG_I2SCDR, 31, 1 },
42329136ad5SPaul Burton },
42429136ad5SPaul Burton
42529136ad5SPaul Burton [JZ4780_CLK_LCD0PIXCLK] = {
42629136ad5SPaul Burton "lcd0pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
42729136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
42829136ad5SPaul Burton JZ4780_CLK_VPLL, -1 },
42929136ad5SPaul Burton .mux = { CGU_REG_LP0CDR, 30, 2 },
4304afe2d1aSHarvey Hunt .div = { CGU_REG_LP0CDR, 0, 1, 8, 28, 27, 26 },
43129136ad5SPaul Burton },
43229136ad5SPaul Burton
43329136ad5SPaul Burton [JZ4780_CLK_LCD1PIXCLK] = {
43429136ad5SPaul Burton "lcd1pixclk", CGU_CLK_MUX | CGU_CLK_DIV,
43529136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
43629136ad5SPaul Burton JZ4780_CLK_VPLL, -1 },
43729136ad5SPaul Burton .mux = { CGU_REG_LP1CDR, 30, 2 },
4384afe2d1aSHarvey Hunt .div = { CGU_REG_LP1CDR, 0, 1, 8, 28, 27, 26 },
43929136ad5SPaul Burton },
44029136ad5SPaul Burton
44129136ad5SPaul Burton [JZ4780_CLK_MSCMUX] = {
44229136ad5SPaul Burton "msc_mux", CGU_CLK_MUX,
44329136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
44429136ad5SPaul Burton .mux = { CGU_REG_MSC0CDR, 30, 2 },
44529136ad5SPaul Burton },
44629136ad5SPaul Burton
44729136ad5SPaul Burton [JZ4780_CLK_MSC0] = {
44829136ad5SPaul Burton "msc0", CGU_CLK_DIV | CGU_CLK_GATE,
44929136ad5SPaul Burton .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
4504afe2d1aSHarvey Hunt .div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
45129136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 3 },
45229136ad5SPaul Burton },
45329136ad5SPaul Burton
45429136ad5SPaul Burton [JZ4780_CLK_MSC1] = {
45529136ad5SPaul Burton "msc1", CGU_CLK_DIV | CGU_CLK_GATE,
45629136ad5SPaul Burton .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
4574afe2d1aSHarvey Hunt .div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
45829136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 11 },
45929136ad5SPaul Burton },
46029136ad5SPaul Burton
46129136ad5SPaul Burton [JZ4780_CLK_MSC2] = {
46229136ad5SPaul Burton "msc2", CGU_CLK_DIV | CGU_CLK_GATE,
46329136ad5SPaul Burton .parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
4644afe2d1aSHarvey Hunt .div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 },
46529136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 12 },
46629136ad5SPaul Burton },
46729136ad5SPaul Burton
46829136ad5SPaul Burton [JZ4780_CLK_UHC] = {
46929136ad5SPaul Burton "uhc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
47029136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
47129136ad5SPaul Burton JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },
47229136ad5SPaul Burton .mux = { CGU_REG_UHCCDR, 30, 2 },
4734afe2d1aSHarvey Hunt .div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 },
47429136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 24 },
47529136ad5SPaul Burton },
47629136ad5SPaul Burton
47729136ad5SPaul Burton [JZ4780_CLK_SSIPLL] = {
47829136ad5SPaul Burton "ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
47929136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
48029136ad5SPaul Burton .mux = { CGU_REG_SSICDR, 30, 1 },
4814afe2d1aSHarvey Hunt .div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
48229136ad5SPaul Burton },
48329136ad5SPaul Burton
48429136ad5SPaul Burton [JZ4780_CLK_SSI] = {
48529136ad5SPaul Burton "ssi", CGU_CLK_MUX,
48629136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_SSIPLL, -1, -1 },
48729136ad5SPaul Burton .mux = { CGU_REG_SSICDR, 31, 1 },
48829136ad5SPaul Burton },
48929136ad5SPaul Burton
49029136ad5SPaul Burton [JZ4780_CLK_CIMMCLK] = {
49129136ad5SPaul Burton "cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
49229136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
49329136ad5SPaul Burton .mux = { CGU_REG_CIMCDR, 31, 1 },
4944afe2d1aSHarvey Hunt .div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 },
49529136ad5SPaul Burton },
49629136ad5SPaul Burton
49729136ad5SPaul Burton [JZ4780_CLK_PCMPLL] = {
49829136ad5SPaul Burton "pcm_pll", CGU_CLK_MUX | CGU_CLK_DIV,
49929136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
50029136ad5SPaul Burton JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },
50129136ad5SPaul Burton .mux = { CGU_REG_PCMCDR, 29, 2 },
5024afe2d1aSHarvey Hunt .div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 },
50329136ad5SPaul Burton },
50429136ad5SPaul Burton
50529136ad5SPaul Burton [JZ4780_CLK_PCM] = {
50629136ad5SPaul Burton "pcm", CGU_CLK_MUX | CGU_CLK_GATE,
50729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, JZ4780_CLK_PCMPLL, -1, -1 },
50829136ad5SPaul Burton .mux = { CGU_REG_PCMCDR, 31, 1 },
50929136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 3 },
51029136ad5SPaul Burton },
51129136ad5SPaul Burton
51229136ad5SPaul Burton [JZ4780_CLK_GPU] = {
51329136ad5SPaul Burton "gpu", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
51429136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
51529136ad5SPaul Burton JZ4780_CLK_EPLL },
51629136ad5SPaul Burton .mux = { CGU_REG_GPUCDR, 30, 2 },
5174afe2d1aSHarvey Hunt .div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 },
51829136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 4 },
51929136ad5SPaul Burton },
52029136ad5SPaul Burton
52129136ad5SPaul Burton [JZ4780_CLK_HDMI] = {
52229136ad5SPaul Burton "hdmi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
52329136ad5SPaul Burton .parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
52429136ad5SPaul Burton JZ4780_CLK_VPLL, -1 },
52529136ad5SPaul Burton .mux = { CGU_REG_HDMICDR, 30, 2 },
5264afe2d1aSHarvey Hunt .div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 },
52729136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 9 },
52829136ad5SPaul Burton },
52929136ad5SPaul Burton
53029136ad5SPaul Burton [JZ4780_CLK_BCH] = {
53129136ad5SPaul Burton "bch", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
53229136ad5SPaul Burton .parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
53329136ad5SPaul Burton JZ4780_CLK_EPLL },
53429136ad5SPaul Burton .mux = { CGU_REG_BCHCDR, 30, 2 },
5354afe2d1aSHarvey Hunt .div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 },
53629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 1 },
53729136ad5SPaul Burton },
53829136ad5SPaul Burton
53982df5b73S周琰杰 (Zhou Yanjie) [JZ4780_CLK_EXCLK_DIV512] = {
54082df5b73S周琰杰 (Zhou Yanjie) "exclk_div512", CGU_CLK_FIXDIV,
54182df5b73S周琰杰 (Zhou Yanjie) .parents = { JZ4780_CLK_EXCLK },
54282df5b73S周琰杰 (Zhou Yanjie) .fixdiv = { 512 },
54382df5b73S周琰杰 (Zhou Yanjie) },
54482df5b73S周琰杰 (Zhou Yanjie)
54582df5b73S周琰杰 (Zhou Yanjie) [JZ4780_CLK_RTC] = {
54682df5b73S周琰杰 (Zhou Yanjie) "rtc_ercs", CGU_CLK_MUX | CGU_CLK_GATE,
54782df5b73S周琰杰 (Zhou Yanjie) .parents = { JZ4780_CLK_EXCLK_DIV512, JZ4780_CLK_RTCLK },
54882df5b73S周琰杰 (Zhou Yanjie) .mux = { CGU_REG_OPCR, 2, 1},
54982df5b73S周琰杰 (Zhou Yanjie) },
55082df5b73S周琰杰 (Zhou Yanjie)
55129136ad5SPaul Burton /* Gate-only clocks */
55229136ad5SPaul Burton
55329136ad5SPaul Burton [JZ4780_CLK_NEMC] = {
55429136ad5SPaul Burton "nemc", CGU_CLK_GATE,
55529136ad5SPaul Burton .parents = { JZ4780_CLK_AHB2, -1, -1, -1 },
55629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 0 },
55729136ad5SPaul Burton },
55829136ad5SPaul Burton
55929136ad5SPaul Burton [JZ4780_CLK_OTG0] = {
56029136ad5SPaul Burton "otg0", CGU_CLK_GATE,
56129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
56229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 2 },
56329136ad5SPaul Burton },
56429136ad5SPaul Burton
56529136ad5SPaul Burton [JZ4780_CLK_SSI0] = {
56629136ad5SPaul Burton "ssi0", CGU_CLK_GATE,
56729136ad5SPaul Burton .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
56829136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 4 },
56929136ad5SPaul Burton },
57029136ad5SPaul Burton
57129136ad5SPaul Burton [JZ4780_CLK_SMB0] = {
57229136ad5SPaul Burton "smb0", CGU_CLK_GATE,
57329136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
57429136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 5 },
57529136ad5SPaul Burton },
57629136ad5SPaul Burton
57729136ad5SPaul Burton [JZ4780_CLK_SMB1] = {
57829136ad5SPaul Burton "smb1", CGU_CLK_GATE,
57929136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
58029136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 6 },
58129136ad5SPaul Burton },
58229136ad5SPaul Burton
58329136ad5SPaul Burton [JZ4780_CLK_SCC] = {
58429136ad5SPaul Burton "scc", CGU_CLK_GATE,
58529136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
58629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 7 },
58729136ad5SPaul Burton },
58829136ad5SPaul Burton
58929136ad5SPaul Burton [JZ4780_CLK_AIC] = {
59029136ad5SPaul Burton "aic", CGU_CLK_GATE,
59129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
59229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 8 },
59329136ad5SPaul Burton },
59429136ad5SPaul Burton
59529136ad5SPaul Burton [JZ4780_CLK_TSSI0] = {
59629136ad5SPaul Burton "tssi0", CGU_CLK_GATE,
59729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
59829136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 9 },
59929136ad5SPaul Burton },
60029136ad5SPaul Burton
60129136ad5SPaul Burton [JZ4780_CLK_OWI] = {
60229136ad5SPaul Burton "owi", CGU_CLK_GATE,
60329136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
60429136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 10 },
60529136ad5SPaul Burton },
60629136ad5SPaul Burton
60729136ad5SPaul Burton [JZ4780_CLK_KBC] = {
60829136ad5SPaul Burton "kbc", CGU_CLK_GATE,
60929136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
61029136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 13 },
61129136ad5SPaul Burton },
61229136ad5SPaul Burton
61329136ad5SPaul Burton [JZ4780_CLK_SADC] = {
61429136ad5SPaul Burton "sadc", CGU_CLK_GATE,
61529136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
61629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 14 },
61729136ad5SPaul Burton },
61829136ad5SPaul Burton
61929136ad5SPaul Burton [JZ4780_CLK_UART0] = {
62029136ad5SPaul Burton "uart0", CGU_CLK_GATE,
62129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
62229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 15 },
62329136ad5SPaul Burton },
62429136ad5SPaul Burton
62529136ad5SPaul Burton [JZ4780_CLK_UART1] = {
62629136ad5SPaul Burton "uart1", CGU_CLK_GATE,
62729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
62829136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 16 },
62929136ad5SPaul Burton },
63029136ad5SPaul Burton
63129136ad5SPaul Burton [JZ4780_CLK_UART2] = {
63229136ad5SPaul Burton "uart2", CGU_CLK_GATE,
63329136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
63429136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 17 },
63529136ad5SPaul Burton },
63629136ad5SPaul Burton
63729136ad5SPaul Burton [JZ4780_CLK_UART3] = {
63829136ad5SPaul Burton "uart3", CGU_CLK_GATE,
63929136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
64029136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 18 },
64129136ad5SPaul Burton },
64229136ad5SPaul Burton
64329136ad5SPaul Burton [JZ4780_CLK_SSI1] = {
64429136ad5SPaul Burton "ssi1", CGU_CLK_GATE,
64529136ad5SPaul Burton .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
64629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 19 },
64729136ad5SPaul Burton },
64829136ad5SPaul Burton
64929136ad5SPaul Burton [JZ4780_CLK_SSI2] = {
65029136ad5SPaul Burton "ssi2", CGU_CLK_GATE,
65129136ad5SPaul Burton .parents = { JZ4780_CLK_SSI, -1, -1, -1 },
65229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 20 },
65329136ad5SPaul Burton },
65429136ad5SPaul Burton
65529136ad5SPaul Burton [JZ4780_CLK_PDMA] = {
65629136ad5SPaul Burton "pdma", CGU_CLK_GATE,
65729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
65829136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 21 },
65929136ad5SPaul Burton },
66029136ad5SPaul Burton
66129136ad5SPaul Burton [JZ4780_CLK_GPS] = {
66229136ad5SPaul Burton "gps", CGU_CLK_GATE,
66329136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
66429136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 22 },
66529136ad5SPaul Burton },
66629136ad5SPaul Burton
66729136ad5SPaul Burton [JZ4780_CLK_MAC] = {
66829136ad5SPaul Burton "mac", CGU_CLK_GATE,
66929136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
67029136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 23 },
67129136ad5SPaul Burton },
67229136ad5SPaul Burton
67329136ad5SPaul Burton [JZ4780_CLK_SMB2] = {
67429136ad5SPaul Burton "smb2", CGU_CLK_GATE,
67529136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
67629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 24 },
67729136ad5SPaul Burton },
67829136ad5SPaul Burton
67929136ad5SPaul Burton [JZ4780_CLK_CIM] = {
68029136ad5SPaul Burton "cim", CGU_CLK_GATE,
68129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
68229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 26 },
68329136ad5SPaul Burton },
68429136ad5SPaul Burton
68529136ad5SPaul Burton [JZ4780_CLK_LCD] = {
68629136ad5SPaul Burton "lcd", CGU_CLK_GATE,
68729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
68829136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 28 },
68929136ad5SPaul Burton },
69029136ad5SPaul Burton
69129136ad5SPaul Burton [JZ4780_CLK_TVE] = {
69229136ad5SPaul Burton "tve", CGU_CLK_GATE,
69329136ad5SPaul Burton .parents = { JZ4780_CLK_LCD, -1, -1, -1 },
69429136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 27 },
69529136ad5SPaul Burton },
69629136ad5SPaul Burton
69729136ad5SPaul Burton [JZ4780_CLK_IPU] = {
69829136ad5SPaul Burton "ipu", CGU_CLK_GATE,
69929136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
70029136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 29 },
70129136ad5SPaul Burton },
70229136ad5SPaul Burton
70329136ad5SPaul Burton [JZ4780_CLK_DDR0] = {
70429136ad5SPaul Burton "ddr0", CGU_CLK_GATE,
70529136ad5SPaul Burton .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
70629136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 30 },
70729136ad5SPaul Burton },
70829136ad5SPaul Burton
70929136ad5SPaul Burton [JZ4780_CLK_DDR1] = {
71029136ad5SPaul Burton "ddr1", CGU_CLK_GATE,
71129136ad5SPaul Burton .parents = { JZ4780_CLK_DDR, -1, -1, -1 },
71229136ad5SPaul Burton .gate = { CGU_REG_CLKGR0, 31 },
71329136ad5SPaul Burton },
71429136ad5SPaul Burton
71529136ad5SPaul Burton [JZ4780_CLK_SMB3] = {
71629136ad5SPaul Burton "smb3", CGU_CLK_GATE,
71729136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
71829136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 0 },
71929136ad5SPaul Burton },
72029136ad5SPaul Burton
72129136ad5SPaul Burton [JZ4780_CLK_TSSI1] = {
72229136ad5SPaul Burton "tssi1", CGU_CLK_GATE,
72329136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
72429136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 1 },
72529136ad5SPaul Burton },
72629136ad5SPaul Burton
72729136ad5SPaul Burton [JZ4780_CLK_COMPRESS] = {
72829136ad5SPaul Burton "compress", CGU_CLK_GATE,
72929136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
73029136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 5 },
73129136ad5SPaul Burton },
73229136ad5SPaul Burton
73329136ad5SPaul Burton [JZ4780_CLK_AIC1] = {
73429136ad5SPaul Burton "aic1", CGU_CLK_GATE,
73529136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
73629136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 6 },
73729136ad5SPaul Burton },
73829136ad5SPaul Burton
73929136ad5SPaul Burton [JZ4780_CLK_GPVLC] = {
74029136ad5SPaul Burton "gpvlc", CGU_CLK_GATE,
74129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
74229136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 7 },
74329136ad5SPaul Burton },
74429136ad5SPaul Burton
74529136ad5SPaul Burton [JZ4780_CLK_OTG1] = {
74629136ad5SPaul Burton "otg1", CGU_CLK_GATE,
74729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
74829136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 8 },
74929136ad5SPaul Burton },
75029136ad5SPaul Burton
75129136ad5SPaul Burton [JZ4780_CLK_UART4] = {
75229136ad5SPaul Burton "uart4", CGU_CLK_GATE,
75329136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
75429136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 10 },
75529136ad5SPaul Burton },
75629136ad5SPaul Burton
75729136ad5SPaul Burton [JZ4780_CLK_AHBMON] = {
75829136ad5SPaul Burton "ahb_mon", CGU_CLK_GATE,
75929136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
76029136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 11 },
76129136ad5SPaul Burton },
76229136ad5SPaul Burton
76329136ad5SPaul Burton [JZ4780_CLK_SMB4] = {
76429136ad5SPaul Burton "smb4", CGU_CLK_GATE,
76529136ad5SPaul Burton .parents = { JZ4780_CLK_PCLK, -1, -1, -1 },
76629136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 12 },
76729136ad5SPaul Burton },
76829136ad5SPaul Burton
76929136ad5SPaul Burton [JZ4780_CLK_DES] = {
77029136ad5SPaul Burton "des", CGU_CLK_GATE,
77129136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
77229136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 13 },
77329136ad5SPaul Burton },
77429136ad5SPaul Burton
77529136ad5SPaul Burton [JZ4780_CLK_X2D] = {
77629136ad5SPaul Burton "x2d", CGU_CLK_GATE,
77729136ad5SPaul Burton .parents = { JZ4780_CLK_EXCLK, -1, -1, -1 },
77829136ad5SPaul Burton .gate = { CGU_REG_CLKGR1, 14 },
77929136ad5SPaul Burton },
78029136ad5SPaul Burton
78129136ad5SPaul Burton [JZ4780_CLK_CORE1] = {
7826673db4fS周琰杰 (Zhou Yanjie) "core1", CGU_CLK_CUSTOM,
78329136ad5SPaul Burton .parents = { JZ4780_CLK_CPU, -1, -1, -1 },
7846673db4fS周琰杰 (Zhou Yanjie) .custom = { &jz4780_core1_ops },
78529136ad5SPaul Burton },
78629136ad5SPaul Burton
78729136ad5SPaul Burton };
78829136ad5SPaul Burton
jz4780_cgu_init(struct device_node * np)78929136ad5SPaul Burton static void __init jz4780_cgu_init(struct device_node *np)
79029136ad5SPaul Burton {
79129136ad5SPaul Burton int retval;
79229136ad5SPaul Burton
79329136ad5SPaul Burton cgu = ingenic_cgu_new(jz4780_cgu_clocks,
79429136ad5SPaul Burton ARRAY_SIZE(jz4780_cgu_clocks), np);
79529136ad5SPaul Burton if (!cgu) {
79629136ad5SPaul Burton pr_err("%s: failed to initialise CGU\n", __func__);
79729136ad5SPaul Burton return;
79829136ad5SPaul Burton }
79929136ad5SPaul Burton
80029136ad5SPaul Burton retval = ingenic_cgu_register_clocks(cgu);
80129136ad5SPaul Burton if (retval) {
80229136ad5SPaul Burton pr_err("%s: failed to register CGU Clocks\n", __func__);
80329136ad5SPaul Burton return;
80429136ad5SPaul Burton }
8052ee93e3cSPaul Cercueil
8062ee93e3cSPaul Cercueil ingenic_cgu_register_syscore_ops(cgu);
80729136ad5SPaul Burton }
80803d570e1SPaul Cercueil CLK_OF_DECLARE_DRIVER(jz4780_cgu, "ingenic,jz4780-cgu", jz4780_cgu_init);
809