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Searched +full:iproc +full:- +full:msi (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/pci/controller/
H A Dpcie-iproc-msi.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/irqchip/irq-msi-lib.h>
10 #include <linux/msi.h>
15 #include "pcie-iproc.h"
35 /* Size of each MSI address region */
53 * struct iproc_msi_grp - iProc MSI group
55 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
58 * @msi: pointer to iProc MSI data
63 struct iproc_msi *msi; member
69 * struct iproc_msi - iProc event queue based MSI
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H A Dpcie-iproc.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2014-2015 Broadcom Corporation
10 * enum iproc_pcie_type - iProc PCIe interface type
11 * @IPROC_PCIE_PAXB_BCMA: BCMA-based host controllers
12 * @IPROC_PCIE_PAXB: PAXB-based host controllers for
14 * @IPROC_PCIE_PAXB_V2: PAXB-based host controllers for Stingray SoCs
15 * @IPROC_PCIE_PAXC: PAXC-based host controllers
16 * @IPROC_PCIE_PAXC_V2: PAXC-based host controllers (second generation)
33 * struct iproc_pcie_ob - iProc PCIe outbound mapping
35 * the iProc PCIe core
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
30 tristate "Altera PCIe MSI feature"
35 Say Y here if you want PCIe MSI support for the Altera FPGA.
36 This MSI driver supports Altera MSI to GIC controller IP.
52 system-on-chips, like the Apple M1. This is required for the USB
53 type-A ports, Ethernet, Wi-Fi, and Bluetooth.
76 This enables the iProc PCIe core controller support for Broadcom's
77 iProc family of SoCs. An appropriate bus interface driver needs
81 tristate "Broadcom iProc PCIe platform bus driver"
87 Say Y here if you want to use the Broadcom iProc PCIe controller
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H A Dpcie-iproc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2014 Hauke Mehrtens <hauke@hauke-m.de>
9 #include <linux/pci-ecam.h>
10 #include <linux/msi.h>
17 #include <linux/irqchip/arm-gic-v3.h>
24 #include "pcie-iproc.h"
91 * struct iproc_pcie_ob_map - iProc PCIe outbound mapping controller-specific
138 * enum iproc_pcie_ib_map_type - iProc PCIe inbound mapping type
150 * struct iproc_pcie_ib_map - iProc PCIe inbound mapping controller-specific
159 * @imap_addr_offset: register offset between the upper and lower 32-bit
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PCIE_CADENCE) += cadence/
3 obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o
4 obj-$(CONFIG_PCI_IXP4XX) += pci-ixp4xx.o
5 obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
6 obj-$(CONFIG_PCI_HYPERV_INTERFACE) += pci-hyperv-intf.o
7 obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
8 obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
9 obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
10 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
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/linux/arch/arm64/boot/dts/broadcom/northstar2/
H A Dns2.dtsi35 #include <dt-bindings/interrupt-controller/arm-gic.h>
36 #include <dt-bindings/clock/bcm-ns2.h>
40 interrupt-parent = <&gic>;
41 #address-cells = <2>;
42 #size-cells = <2>;
45 #address-cells = <2>;
46 #size-cells = <0>;
50 compatible = "arm,cortex-a57";
52 enable-method = "psci";
53 next-level-cache = <&CLUSTER0_L2>;
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/linux/arch/arm/boot/dts/broadcom/
H A Dbcm-hr2.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
39 interrupt-parent = <&gic>;
40 #address-cells = <1>;
41 #size-cells = <1>;
44 #address-cells = <1>;
45 #size-cells = <0>;
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
56 compatible = "arm,cortex-a9-pmu";
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H A Dbcm-nsp.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-nsp.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
53 #address-cells = <1>;
54 #size-cells = <0>;
58 compatible = "arm,cortex-a9";
59 next-level-cache = <&L2>;
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H A Dbcm-cygnus.dtsi33 #include <dt-bindings/interrupt-controller/arm-gic.h>
34 #include <dt-bindings/interrupt-controller/irq.h>
35 #include <dt-bindings/clock/bcm-cygnus.h>
38 #address-cells = <1>;
39 #size-cells = <1>;
42 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <0>;
59 compatible = "arm,cortex-a9";
60 next-level-cache = <&L2>;
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/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray-fs4.dtsi4 * Copyright(c) 2016-2017 Broadcom. All rights reserved.
34 compatible = "simple-bus";
35 #address-cells = <1>;
36 #size-cells = <1>;
40 compatible = "brcm,iproc-flexrm-mbox";
42 msi-parent = <&gic_its 0x4100>;
43 #mbox-cells = <3>;
44 dma-coherent;
48 compatible = "brcm,iproc-flexrm-mbox";
50 dma-coherent;
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H A Dstingray.dtsi4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
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H A Dstingray-pcie.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
7 compatible = "brcm,iproc-pcie-paxc-v2";
9 linux,pci-domain = <8>;
11 bus-range = <0x0 0x1>;
13 #address-cells = <3>;
14 #size-cells = <2>;
18 dma-coherent;
20 msi-map = <0x100 &gic_its 0x2000 0x1>, /* PF0 */
21 <0x108 &gic_its 0x2040 0x8>, /* PF0-VF0-7 */
23 <0x110 &gic_its 0x20c8 0x8>, /* PF1-VF8-15 */
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/linux/drivers/mailbox/
H A Dbcm-flexrm-mailbox.c1 // SPDX-License-Identifier: GPL-2.0-only
23 #include <linux/dma-mapping.h>
30 #include <linux/mailbox/brcm-message.h>
32 #include <linux/msi.h>
50 (!((addr) & ((0x1 << RING_BD_ALIGN_ORDER) - 1)))
66 /* Per-Ring register offsets */
316 return -EIO; in flexrm_cmpl_desc_to_error()
322 return -ETIMEDOUT; in flexrm_cmpl_desc_to_error()
407 * by one or more non-HEADER descriptors (SRC, SRCT, MSRC, DST, in flexrm_enqueue_desc()
408 * DSTT, MDST, IMM, and IMMT). The number of non-HEADER descriptors in flexrm_enqueue_desc()
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/linux/drivers/pci/
H A Dquirks.c1 // SPDX-License-Identifier: GPL-2.0
3 * This file contains work-arounds for many known PCI hardware bugs.
5 * should be handled in arch-specific code.
22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */
41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) in pcie_lbms_seen()
102 int ret = -ENOTTY; in pcie_failed_link_retrain()
105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) in pcie_failed_link_retrain()
112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); in pcie_failed_link_retrain()
173 if ((f->class == (u32) (dev->class >> f->class_shift) || in pci_do_fixups()
174 f->class == (u32) PCI_ANY_ID) && in pci_do_fixups()
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/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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