Lines Matching +full:iproc +full:- +full:msi
1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/irqchip/irq-msi-lib.h>
10 #include <linux/msi.h>
15 #include "pcie-iproc.h"
35 /* Size of each MSI address region */
53 * struct iproc_msi_grp - iProc MSI group
55 * One MSI group is allocated per GIC interrupt, serviced by one iProc MSI
58 * @msi: pointer to iProc MSI data
63 struct iproc_msi *msi; member
69 * struct iproc_msi - iProc event queue based MSI
71 * Only meant to be used on platforms without MSI support integrated into the
74 * @pcie: pointer to iProc PCIe data
75 * @reg_offsets: MSI register offsets
76 * @grps: MSI groups
79 * @has_inten_reg: indicates the MSI interrupt enable register needs to be
81 * @bitmap: MSI vector bitmap
82 * @bitmap_lock: lock to protect access to the MSI bitmap
83 * @nr_msi_vecs: total number of MSI vectors
85 * @nr_eq_region: required number of 4K aligned memory region for MSI event
87 * @nr_msi_region: required number of 4K aligned address region for MSI posted
89 * @eq_cpu: pointer to allocated memory region for MSI event queues
90 * @eq_dma: DMA address of MSI event queues
91 * @msi_addr: MSI address
127 static inline u32 iproc_msi_read_reg(struct iproc_msi *msi, in iproc_msi_read_reg() argument
131 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_read_reg()
133 return readl_relaxed(pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_read_reg()
136 static inline void iproc_msi_write_reg(struct iproc_msi *msi, in iproc_msi_write_reg() argument
140 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_write_reg()
142 writel_relaxed(val, pcie->base + msi->reg_offsets[eq][reg]); in iproc_msi_write_reg()
145 static inline u32 hwirq_to_group(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_group() argument
147 return (hwirq % msi->nr_irqs); in hwirq_to_group()
150 static inline unsigned int iproc_msi_addr_offset(struct iproc_msi *msi, in iproc_msi_addr_offset() argument
153 if (msi->nr_msi_region > 1) in iproc_msi_addr_offset()
154 return hwirq_to_group(msi, hwirq) * MSI_MEM_REGION_SIZE; in iproc_msi_addr_offset()
156 return hwirq_to_group(msi, hwirq) * sizeof(u32); in iproc_msi_addr_offset()
159 static inline unsigned int iproc_msi_eq_offset(struct iproc_msi *msi, u32 eq) in iproc_msi_eq_offset() argument
161 if (msi->nr_eq_region > 1) in iproc_msi_eq_offset()
176 .prefix = "iProc-",
180 * In iProc PCIe core, each MSI group is serviced by a GIC interrupt and a
181 * dedicated event queue. Each MSI group can support up to 64 MSI vectors.
183 * The number of MSI groups varies between different iProc SoCs. The total
184 * number of CPU cores also varies. To support MSI IRQ affinity, we
185 * distribute GIC interrupts across all available CPUs. MSI vector is moved
189 * - the number of MSI groups is M
190 * - the number of CPU cores is N
191 * - M is always a multiple of N
193 * Total number of raw MSI vectors = M * 64
194 * Total number of supported MSI vectors = (M * 64) / N
196 static inline int hwirq_to_cpu(struct iproc_msi *msi, unsigned long hwirq) in hwirq_to_cpu() argument
198 return (hwirq % msi->nr_cpus); in hwirq_to_cpu()
201 static inline unsigned long hwirq_to_canonical_hwirq(struct iproc_msi *msi, in hwirq_to_canonical_hwirq() argument
204 return (hwirq - hwirq_to_cpu(msi, hwirq)); in hwirq_to_canonical_hwirq()
210 struct iproc_msi *msi = irq_data_get_irq_chip_data(data); in iproc_msi_irq_set_affinity() local
215 curr_cpu = hwirq_to_cpu(msi, data->hwirq); in iproc_msi_irq_set_affinity()
219 /* steer MSI to the target CPU */ in iproc_msi_irq_set_affinity()
220 data->hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq) + target_cpu; in iproc_msi_irq_set_affinity()
232 struct iproc_msi *msi = irq_data_get_irq_chip_data(data); in iproc_msi_irq_compose_msi_msg() local
235 addr = msi->msi_addr + iproc_msi_addr_offset(msi, data->hwirq); in iproc_msi_irq_compose_msi_msg()
236 msg->address_lo = lower_32_bits(addr); in iproc_msi_irq_compose_msi_msg()
237 msg->address_hi = upper_32_bits(addr); in iproc_msi_irq_compose_msi_msg()
238 msg->data = data->hwirq << 5; in iproc_msi_irq_compose_msi_msg()
242 .name = "MSI",
251 struct iproc_msi *msi = domain->host_data; in iproc_msi_irq_domain_alloc() local
254 if (msi->nr_cpus > 1 && nr_irqs > 1) in iproc_msi_irq_domain_alloc()
255 return -EINVAL; in iproc_msi_irq_domain_alloc()
257 mutex_lock(&msi->bitmap_lock); in iproc_msi_irq_domain_alloc()
260 * Allocate 'nr_irqs' multiplied by 'nr_cpus' number of MSI vectors in iproc_msi_irq_domain_alloc()
263 hwirq = bitmap_find_free_region(msi->bitmap, msi->nr_msi_vecs, in iproc_msi_irq_domain_alloc()
264 order_base_2(msi->nr_cpus * nr_irqs)); in iproc_msi_irq_domain_alloc()
266 mutex_unlock(&msi->bitmap_lock); in iproc_msi_irq_domain_alloc()
269 return -ENOSPC; in iproc_msi_irq_domain_alloc()
274 domain->host_data, handle_simple_irq, in iproc_msi_irq_domain_alloc()
285 struct iproc_msi *msi = irq_data_get_irq_chip_data(data); in iproc_msi_irq_domain_free() local
288 mutex_lock(&msi->bitmap_lock); in iproc_msi_irq_domain_free()
290 hwirq = hwirq_to_canonical_hwirq(msi, data->hwirq); in iproc_msi_irq_domain_free()
291 bitmap_release_region(msi->bitmap, hwirq, in iproc_msi_irq_domain_free()
292 order_base_2(msi->nr_cpus * nr_irqs)); in iproc_msi_irq_domain_free()
294 mutex_unlock(&msi->bitmap_lock); in iproc_msi_irq_domain_free()
304 static inline u32 decode_msi_hwirq(struct iproc_msi *msi, u32 eq, u32 head) in decode_msi_hwirq() argument
310 offs = iproc_msi_eq_offset(msi, eq) + head * sizeof(u32); in decode_msi_hwirq()
311 msg = (u32 __iomem *)(msi->eq_cpu + offs); in decode_msi_hwirq()
316 * Since we have multiple hwirq mapped to a single MSI vector, in decode_msi_hwirq()
320 return hwirq_to_canonical_hwirq(msi, hwirq); in decode_msi_hwirq()
327 struct iproc_msi *msi; in iproc_msi_handler() local
334 msi = grp->msi; in iproc_msi_handler()
335 eq = grp->eq; in iproc_msi_handler()
338 * iProc MSI event queue is tracked by head and tail pointers. Head in iproc_msi_handler()
339 * pointer indicates the next entry (MSI data) to be consumed by SW in in iproc_msi_handler()
340 * the queue and needs to be updated by SW. iProc MSI core uses the in iproc_msi_handler()
343 * Entries between head and tail pointers contain valid MSI data. MSI in iproc_msi_handler()
345 * pointer is updated by the iProc MSI core. in iproc_msi_handler()
347 head = iproc_msi_read_reg(msi, IPROC_MSI_EQ_HEAD, in iproc_msi_handler()
350 tail = iproc_msi_read_reg(msi, IPROC_MSI_EQ_TAIL, in iproc_msi_handler()
354 * Figure out total number of events (MSI data) to be in iproc_msi_handler()
358 (EQ_LEN - (head - tail)) : (tail - head); in iproc_msi_handler()
363 while (nr_events--) { in iproc_msi_handler()
364 hwirq = decode_msi_hwirq(msi, eq, head); in iproc_msi_handler()
365 generic_handle_domain_irq(msi->inner_domain, hwirq); in iproc_msi_handler()
375 iproc_msi_write_reg(msi, IPROC_MSI_EQ_HEAD, eq, head); in iproc_msi_handler()
386 static void iproc_msi_enable(struct iproc_msi *msi) in iproc_msi_enable() argument
392 for (i = 0; i < msi->nr_eq_region; i++) { in iproc_msi_enable()
393 dma_addr_t addr = msi->eq_dma + (i * EQ_MEM_REGION_SIZE); in iproc_msi_enable()
395 iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE, i, in iproc_msi_enable()
397 iproc_msi_write_reg(msi, IPROC_MSI_EQ_PAGE_UPPER, i, in iproc_msi_enable()
401 /* Program address region for MSI posted writes */ in iproc_msi_enable()
402 for (i = 0; i < msi->nr_msi_region; i++) { in iproc_msi_enable()
403 phys_addr_t addr = msi->msi_addr + (i * MSI_MEM_REGION_SIZE); in iproc_msi_enable()
405 iproc_msi_write_reg(msi, IPROC_MSI_PAGE, i, in iproc_msi_enable()
407 iproc_msi_write_reg(msi, IPROC_MSI_PAGE_UPPER, i, in iproc_msi_enable()
411 for (eq = 0; eq < msi->nr_irqs; eq++) { in iproc_msi_enable()
412 /* Enable MSI event queue */ in iproc_msi_enable()
415 iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val); in iproc_msi_enable()
418 * Some legacy platforms require the MSI interrupt enable in iproc_msi_enable()
421 if (msi->has_inten_reg) { in iproc_msi_enable()
422 val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq); in iproc_msi_enable()
424 iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val); in iproc_msi_enable()
429 static void iproc_msi_disable(struct iproc_msi *msi) in iproc_msi_disable() argument
433 for (eq = 0; eq < msi->nr_irqs; eq++) { in iproc_msi_disable()
434 if (msi->has_inten_reg) { in iproc_msi_disable()
435 val = iproc_msi_read_reg(msi, IPROC_MSI_INTS_EN, eq); in iproc_msi_disable()
437 iproc_msi_write_reg(msi, IPROC_MSI_INTS_EN, eq, val); in iproc_msi_disable()
440 val = iproc_msi_read_reg(msi, IPROC_MSI_CTRL, eq); in iproc_msi_disable()
443 iproc_msi_write_reg(msi, IPROC_MSI_CTRL, eq, val); in iproc_msi_disable()
448 struct iproc_msi *msi) in iproc_msi_alloc_domains() argument
453 .host_data = msi, in iproc_msi_alloc_domains()
454 .size = msi->nr_msi_vecs, in iproc_msi_alloc_domains()
457 msi->inner_domain = msi_create_parent_irq_domain(&info, &iproc_msi_parent_ops); in iproc_msi_alloc_domains()
458 if (!msi->inner_domain) in iproc_msi_alloc_domains()
459 return -ENOMEM; in iproc_msi_alloc_domains()
464 static void iproc_msi_free_domains(struct iproc_msi *msi) in iproc_msi_free_domains() argument
466 if (msi->inner_domain) in iproc_msi_free_domains()
467 irq_domain_remove(msi->inner_domain); in iproc_msi_free_domains()
470 static void iproc_msi_irq_free(struct iproc_msi *msi, unsigned int cpu) in iproc_msi_irq_free() argument
474 for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) { in iproc_msi_irq_free()
475 irq_set_chained_handler_and_data(msi->grps[i].gic_irq, in iproc_msi_irq_free()
480 static int iproc_msi_irq_setup(struct iproc_msi *msi, unsigned int cpu) in iproc_msi_irq_setup() argument
484 struct iproc_pcie *pcie = msi->pcie; in iproc_msi_irq_setup()
486 for (i = cpu; i < msi->nr_irqs; i += msi->nr_cpus) { in iproc_msi_irq_setup()
487 irq_set_chained_handler_and_data(msi->grps[i].gic_irq, in iproc_msi_irq_setup()
489 &msi->grps[i]); in iproc_msi_irq_setup()
494 ret = irq_set_affinity(msi->grps[i].gic_irq, mask); in iproc_msi_irq_setup()
496 dev_err(pcie->dev, in iproc_msi_irq_setup()
498 msi->grps[i].gic_irq); in iproc_msi_irq_setup()
501 dev_err(pcie->dev, "failed to alloc CPU mask\n"); in iproc_msi_irq_setup()
502 ret = -EINVAL; in iproc_msi_irq_setup()
507 iproc_msi_irq_free(msi, cpu); in iproc_msi_irq_setup()
517 struct iproc_msi *msi; in iproc_msi_init() local
521 if (!of_device_is_compatible(node, "brcm,iproc-msi")) in iproc_msi_init()
522 return -ENODEV; in iproc_msi_init()
524 if (!of_property_read_bool(node, "msi-controller")) in iproc_msi_init()
525 return -ENODEV; in iproc_msi_init()
527 if (pcie->msi) in iproc_msi_init()
528 return -EBUSY; in iproc_msi_init()
530 msi = devm_kzalloc(pcie->dev, sizeof(*msi), GFP_KERNEL); in iproc_msi_init()
531 if (!msi) in iproc_msi_init()
532 return -ENOMEM; in iproc_msi_init()
534 msi->pcie = pcie; in iproc_msi_init()
535 pcie->msi = msi; in iproc_msi_init()
536 msi->msi_addr = pcie->base_addr; in iproc_msi_init()
537 mutex_init(&msi->bitmap_lock); in iproc_msi_init()
538 msi->nr_cpus = num_possible_cpus(); in iproc_msi_init()
540 if (msi->nr_cpus == 1) in iproc_msi_init()
543 msi->nr_irqs = of_irq_count(node); in iproc_msi_init()
544 if (!msi->nr_irqs) { in iproc_msi_init()
545 dev_err(pcie->dev, "found no MSI GIC interrupt\n"); in iproc_msi_init()
546 return -ENODEV; in iproc_msi_init()
549 if (msi->nr_irqs > NR_HW_IRQS) { in iproc_msi_init()
550 dev_warn(pcie->dev, "too many MSI GIC interrupts defined %d\n", in iproc_msi_init()
551 msi->nr_irqs); in iproc_msi_init()
552 msi->nr_irqs = NR_HW_IRQS; in iproc_msi_init()
555 if (msi->nr_irqs < msi->nr_cpus) { in iproc_msi_init()
556 dev_err(pcie->dev, in iproc_msi_init()
557 "not enough GIC interrupts for MSI affinity\n"); in iproc_msi_init()
558 return -EINVAL; in iproc_msi_init()
561 if (msi->nr_irqs % msi->nr_cpus != 0) { in iproc_msi_init()
562 msi->nr_irqs -= msi->nr_irqs % msi->nr_cpus; in iproc_msi_init()
563 dev_warn(pcie->dev, "Reducing number of interrupts to %d\n", in iproc_msi_init()
564 msi->nr_irqs); in iproc_msi_init()
567 switch (pcie->type) { in iproc_msi_init()
570 msi->reg_offsets = iproc_msi_reg_paxb; in iproc_msi_init()
571 msi->nr_eq_region = 1; in iproc_msi_init()
572 msi->nr_msi_region = 1; in iproc_msi_init()
575 msi->reg_offsets = iproc_msi_reg_paxc; in iproc_msi_init()
576 msi->nr_eq_region = msi->nr_irqs; in iproc_msi_init()
577 msi->nr_msi_region = msi->nr_irqs; in iproc_msi_init()
580 dev_err(pcie->dev, "incompatible iProc PCIe interface\n"); in iproc_msi_init()
581 return -EINVAL; in iproc_msi_init()
584 msi->has_inten_reg = of_property_read_bool(node, "brcm,pcie-msi-inten"); in iproc_msi_init()
586 msi->nr_msi_vecs = msi->nr_irqs * EQ_LEN; in iproc_msi_init()
587 msi->bitmap = devm_bitmap_zalloc(pcie->dev, msi->nr_msi_vecs, in iproc_msi_init()
589 if (!msi->bitmap) in iproc_msi_init()
590 return -ENOMEM; in iproc_msi_init()
592 msi->grps = devm_kcalloc(pcie->dev, msi->nr_irqs, sizeof(*msi->grps), in iproc_msi_init()
594 if (!msi->grps) in iproc_msi_init()
595 return -ENOMEM; in iproc_msi_init()
597 for (i = 0; i < msi->nr_irqs; i++) { in iproc_msi_init()
601 dev_err(pcie->dev, "unable to parse/map interrupt\n"); in iproc_msi_init()
602 ret = -ENODEV; in iproc_msi_init()
605 msi->grps[i].gic_irq = irq; in iproc_msi_init()
606 msi->grps[i].msi = msi; in iproc_msi_init()
607 msi->grps[i].eq = i; in iproc_msi_init()
611 msi->eq_cpu = dma_alloc_coherent(pcie->dev, in iproc_msi_init()
612 msi->nr_eq_region * EQ_MEM_REGION_SIZE, in iproc_msi_init()
613 &msi->eq_dma, GFP_KERNEL); in iproc_msi_init()
614 if (!msi->eq_cpu) { in iproc_msi_init()
615 ret = -ENOMEM; in iproc_msi_init()
619 ret = iproc_msi_alloc_domains(node, msi); in iproc_msi_init()
621 dev_err(pcie->dev, "failed to create MSI domains\n"); in iproc_msi_init()
626 ret = iproc_msi_irq_setup(msi, cpu); in iproc_msi_init()
631 iproc_msi_enable(msi); in iproc_msi_init()
637 iproc_msi_irq_free(msi, cpu); in iproc_msi_init()
638 iproc_msi_free_domains(msi); in iproc_msi_init()
641 dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE, in iproc_msi_init()
642 msi->eq_cpu, msi->eq_dma); in iproc_msi_init()
645 for (i = 0; i < msi->nr_irqs; i++) { in iproc_msi_init()
646 if (msi->grps[i].gic_irq) in iproc_msi_init()
647 irq_dispose_mapping(msi->grps[i].gic_irq); in iproc_msi_init()
649 pcie->msi = NULL; in iproc_msi_init()
656 struct iproc_msi *msi = pcie->msi; in iproc_msi_exit() local
659 if (!msi) in iproc_msi_exit()
662 iproc_msi_disable(msi); in iproc_msi_exit()
665 iproc_msi_irq_free(msi, cpu); in iproc_msi_exit()
667 iproc_msi_free_domains(msi); in iproc_msi_exit()
669 dma_free_coherent(pcie->dev, msi->nr_eq_region * EQ_MEM_REGION_SIZE, in iproc_msi_exit()
670 msi->eq_cpu, msi->eq_dma); in iproc_msi_exit()
672 for (i = 0; i < msi->nr_irqs; i++) { in iproc_msi_exit()
673 if (msi->grps[i].gic_irq) in iproc_msi_exit()
674 irq_dispose_mapping(msi->grps[i].gic_irq); in iproc_msi_exit()