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/freebsd/sys/contrib/device-tree/Bindings/iommu/
H A Dqcom,iommu.txt1 * QCOM IOMMU v1 Implementation
3 Qualcomm "B" family devices which are not compatible with arm-smmu have
4 a similar looking IOMMU but without access to the global register space,
6 to non-secure vs secure interrupt line.
10 - compatible : Should be one of:
12 "qcom,msm8916-iommu"
13 "qcom,msm8953-iommu"
15 Followed by "qcom,msm-iommu-v1".
17 - clock-names : Should be a pair of "iface" (required for IOMMUs
21 - clocks : Phandles for respective clocks described by
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H A Dqcom,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
10 - Konrad Dybcio <konradybcio@kernel.org>
13 Qualcomm "B" family devices which are not compatible with arm-smmu have
14 a similar looking IOMMU, but without access to the global register space
16 to non-secure vs secure interrupt line.
21 - items:
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H A Dsprd,iommu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Unisoc IOMMU and Multi-media MMU
11 - Chunyan Zhang <zhang.lyra@gmail.com>
16 - sprd,iommu-v1
18 "#iommu-cells":
21 Unisoc IOMMUs are all single-master IOMMU devices, therefore no
24 Documentation/devicetree/bindings/iommu/iommu.txt
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H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsc8280xp-el2.dtso1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
12 zap-shader {
18 * When running under QHEE, this IOMMU is controlled by the firmware,
23 iommu-map = <0 &pcie_smmu 0x20000 0x10000>;
27 iommu-map = <0 &pcie_smmu 0x30000 0x10000>;
31 iommu-map = <0 &pcie_smmu 0x40000 0x10000>;
35 iommu-map = <0 &pcie_smmu 0x50000 0x10000>;
39 iommu-map = <0 &pcie_smmu 0x60000 0x10000>;
H A Dx1-el2.dtso1 // SPDX-License-Identifier: BSD-3-Clause
7 /dts-v1/;
16 * When running under Gunyah, this IOMMU is controlled by the firmware,
25 iommu-map = <0 &pcie_smmu 0x30000 0x10000>;
26 msi-map = <0 &gic_its 0xb0000 0x10000>;
30 iommu-map = <0 &pcie_smmu 0x40000 0x10000>;
34 iommu-map = <0 &pcie_smmu 0x50000 0x10000>;
35 msi-map = <0 &gic_its 0xd0000 0x10000>;
39 iommu-map = <0 &pcie_smmu 0x60000 0x10000>;
H A Dmsm8917.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
4 #include <dt-bindings/clock/qcom,gcc-msm8917.h>
5 #include <dt-bindings/clock/qcom,rpmcc.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/power/qcom-rpmpd.h>
8 #include <dt-bindings/thermal/thermal.h>
11 interrupt-parent = <&intc>;
13 #address-cells = <2>;
14 #size-cells = <2>;
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H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
10 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/power/qcom-rpmpd.h>
18 interrupt-parent = <&intc>;
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H A Dmsm8953.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
4 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8953.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interconnect/qcom,msm8953.h>
9 #include <dt-bindings/interconnect/qcom,rpm-icc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
12 #include <dt-bindings/soc/qcom,apr.h>
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H A Dmsm8939.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
4 * Copyright (c) 2020-2023, Linaro Limited
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-msm8939.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8939.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/reset/qcom,gcc-msm8939.h>
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H A Dmsm8916.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/arm/coresight-cti-dt.h>
7 #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
8 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8916.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom-rpmpd.h>
13 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Djuno-base.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include "juno-clocks.dtsi"
3 #include "juno-motherboard.dtsi"
11 compatible = "arm,armv7-timer-mem";
13 #address-cells = <1>;
14 #size-cells = <1>;
18 frame-number = <1>;
30 #mbox-cells = <1>;
32 clock-names = "apb_pclk";
35 smmu_gpu: iommu@2b400000 {
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H A Dmorello-sdp.dts1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
6 /dts-v1/;
11 compatible = "arm,morello-sdp", "arm,morello";
18 stdout-path = "serial0:115200n8";
21 dpu_aclk: clock-350000000 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <350000000>;
26 clock-output-names = "aclk";
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/freebsd/sys/contrib/device-tree/src/arm/qcom/
H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
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/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dp5020si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5020-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp3041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p3041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp2041si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p2041-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp5040si-post.dtsi4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10000 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10000 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10000 0>;
51 compatible = "fsl,p5040-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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H A Dp4080si-post.dtsi4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
36 compatible = "fsl,bman-fbpr";
37 alloc-ranges = <0 0 0x10 0>;
41 compatible = "fsl,qman-fqd";
42 alloc-ranges = <0 0 0x10 0>;
46 compatible = "fsl,qman-pfdr";
47 alloc-ranges = <0 0 0x10 0>;
51 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
53 #address-cells = <2>;
54 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/
H A Dpamu.txt5 The PAMU is an I/O MMU that provides device-to-memory access control and
10 - compatible : <string>
11 First entry is a version-specific string, such as
12 "fsl,pamu-v1.0". The second is "fsl,pamu".
13 - ranges : <prop-encoded-array>
18 PAMU v1.0, on an SOC that has five PAMU devices, the size
20 - interrupts : <prop-encoded-array>
25 - #address-cells: <u32>
27 - #size-cells : <u32>
31 - reg : <prop-encoded-array>
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H A Draideng.txt3 RAID Engine nodes are defined to describe on-chip RAID accelerators. Each RAID
11 - compatible: Should contain "fsl,raideng-v1.0" as the value
15 - reg: offset and length of the register set for the device
16 - ranges: standard ranges property specifying the translation
22 compatible = "fsl,raideng-v1.0";
23 #address-cells = <1>;
24 #size-cell
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/freebsd/sys/amd64/vmm/amd/
H A Damdvi_priv.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
40 ((1 << (((n) - (m)) + 1)) - 1))
43 * IOMMU PCI capability.
52 * IOMMU extended features.
57 #define AMDVI_EX_FEA_NXSUP BIT(3) /* No-execute. */
68 * NOTE: Must be 256-bits/32 bytes aligned.
112 * IOMMU command entry.
127 #define AMDVI_PREFETCH_PAGES_OPCODE 0x6 /* Prefetch IOMMU pages. */
151 * IOMMU event entry.
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/freebsd/sys/dev/virtio/
H A Dvirtio_config.h1 /*-
68 /* v1.0 compliant. */
72 * If clear - device has the IOMMU bypass quirk feature.
73 * If set - use platform tools to detect the IOMMU.
83 * rest are per-device feature bits.
/freebsd/sys/contrib/device-tree/src/arm/mediatek/
H A Dmt2701.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/clock/mt2701-clk.h>
9 #include <dt-bindings/phy/phy.h>
10 #include <dt-bindings/power/mt2701-power.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/memory/mt2701-larb-port.h>
14 #include <dt-bindings/reset/mt2701-resets.h>
15 #include "mt2701-pinfunc.h"
18 #address-cells = <2>;
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/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dsamsung,exynos4212-fimc-is.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/media/samsung,exynos4212-fim
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