Lines Matching +full:iommu +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for Rockchip
5 * Module Authors: Simon Xue <xxm@rock-chips.com>
13 #include <linux/dma-mapping.h>
17 #include <linux/iommu.h>
29 #include "iommu-pages.h"
38 #define RK_MMU_INT_CLEAR 0x18 /* Acknowledge and re-arm irq */
62 #define RK_MMU_CMD_DISABLE_STALL 3 /* Stop stall re-enables paging */
94 /* list of clocks required by IOMMU */
115 struct iommu_device iommu; member
117 struct iommu_domain *domain; /* domain to which iommu is attached */
121 struct device_link *link; /* runtime PM link from IOMMU to master */
122 struct rk_iommu *iommu; member
143 * The Rockchip rk3288 iommu uses a 2-level page table.
145 * The DT consists of 1024 4-byte Directory Table Entries (DTEs), each pointing
148 * Each PT consists of 1024 4-byte Page Table Entries (PTEs), each pointing to
151 * The DT and each PT fits in a single 4 KB page (4-bytes * 1024 entries).
152 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
158 * MMU_DTE_ADDR -> +-----+
160 * +-----+ PT
161 * | DTE | -> +-----+
162 * +-----+ | | Memory
163 * | | +-----+ Page
164 * | | | PTE | -> +-----+
165 * +-----+ +-----+ | |
168 * +-----+ | |
171 * +-----+
176 * +---------------------+-----------+-+
178 * +---------------------+-----------+-+
179 * 31:12 - PT address (PTs always starts on a 4 KB boundary)
180 * 11: 1 - Reserved
181 * 0 - 1 if PT @ PT address is valid
193 * 31:12 - PT address bit 31:0
194 * 11: 8 - PT address bit 35:32
195 * 7: 4 - PT address bit 39:36
196 * 3: 1 - Reserved
197 * 0 - 1 if PT @ PT address is valid
239 * +---------------------+---+-------+-+
241 * +---------------------+---+-------+-+
242 * 31:12 - Page address (Pages always start on a 4 KB boundary)
243 * 11: 9 - Reserved
244 * 8: 1 - Flags
245 * 8 - Read allocate - allocate cache space on read misses
246 * 7 - Read cache - enable cache & prefetch of data
247 * 6 - Write buffer - enable delaying writes on their way to memory
248 * 5 - Write allocate - allocate cache space on write misses
249 * 4 - Write cache - different writes can be merged together
250 * 3 - Override cache attributes
251 * if 1, bits 4-8 control cache attributes
253 * 2 - Writable
254 * 1 - Readable
255 * 0 - 1 if Page @ Page address is valid
280 * 31:12 - Page address bit 31:0
281 * 11: 8 - Page address bit 35:32
282 * 7: 4 - Page address bit 39:36
283 * 3 - Security
284 * 2 - Writable
285 * 1 - Readable
286 * 0 - 1 if Page @ Page address is valid
305 * rk3288 iova (IOMMU Virtual Address) format
307 * +-----------+-----------+-------------+
309 * +-----------+-----------+-------------+
310 * 31:22 - DTE index - index of DTE in DT
311 * 21:12 - PTE index - index of PTE in PT @ DTE.pt_address
312 * 11: 0 - Page offset - offset into page @ PTE.page_address
346 static void rk_iommu_command(struct rk_iommu *iommu, u32 command) in rk_iommu_command() argument
350 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_command()
351 writel(command, iommu->bases[i] + RK_MMU_COMMAND); in rk_iommu_command()
358 static void rk_iommu_zap_lines(struct rk_iommu *iommu, dma_addr_t iova_start, in rk_iommu_zap_lines() argument
367 for (i = 0; i < iommu->num_mmu; i++) { in rk_iommu_zap_lines()
371 rk_iommu_write(iommu->bases[i], RK_MMU_ZAP_ONE_LINE, iova); in rk_iommu_zap_lines()
375 static bool rk_iommu_is_stall_active(struct rk_iommu *iommu) in rk_iommu_is_stall_active() argument
380 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_is_stall_active()
381 active &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_stall_active()
387 static bool rk_iommu_is_paging_enabled(struct rk_iommu *iommu) in rk_iommu_is_paging_enabled() argument
392 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_is_paging_enabled()
393 enable &= !!(rk_iommu_read(iommu->bases[i], RK_MMU_STATUS) & in rk_iommu_is_paging_enabled()
399 static bool rk_iommu_is_reset_done(struct rk_iommu *iommu) in rk_iommu_is_reset_done() argument
404 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_is_reset_done()
405 done &= rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR) == 0; in rk_iommu_is_reset_done()
410 static int rk_iommu_enable_stall(struct rk_iommu *iommu) in rk_iommu_enable_stall() argument
415 if (rk_iommu_is_stall_active(iommu)) in rk_iommu_enable_stall()
419 if (!rk_iommu_is_paging_enabled(iommu)) in rk_iommu_enable_stall()
422 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_STALL); in rk_iommu_enable_stall()
424 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, in rk_iommu_enable_stall()
428 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_enable_stall()
429 dev_err(iommu->dev, "Enable stall request timed out, status: %#08x\n", in rk_iommu_enable_stall()
430 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_stall()
435 static int rk_iommu_disable_stall(struct rk_iommu *iommu) in rk_iommu_disable_stall() argument
440 if (!rk_iommu_is_stall_active(iommu)) in rk_iommu_disable_stall()
443 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_STALL); in rk_iommu_disable_stall()
445 ret = readx_poll_timeout(rk_iommu_is_stall_active, iommu, val, in rk_iommu_disable_stall()
449 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_disable_stall()
450 dev_err(iommu->dev, "Disable stall request timed out, status: %#08x\n", in rk_iommu_disable_stall()
451 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_stall()
456 static int rk_iommu_enable_paging(struct rk_iommu *iommu) in rk_iommu_enable_paging() argument
461 if (rk_iommu_is_paging_enabled(iommu)) in rk_iommu_enable_paging()
464 rk_iommu_command(iommu, RK_MMU_CMD_ENABLE_PAGING); in rk_iommu_enable_paging()
466 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, in rk_iommu_enable_paging()
470 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_enable_paging()
471 dev_err(iommu->dev, "Enable paging request timed out, status: %#08x\n", in rk_iommu_enable_paging()
472 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_enable_paging()
477 static int rk_iommu_disable_paging(struct rk_iommu *iommu) in rk_iommu_disable_paging() argument
482 if (!rk_iommu_is_paging_enabled(iommu)) in rk_iommu_disable_paging()
485 rk_iommu_command(iommu, RK_MMU_CMD_DISABLE_PAGING); in rk_iommu_disable_paging()
487 ret = readx_poll_timeout(rk_iommu_is_paging_enabled, iommu, val, in rk_iommu_disable_paging()
491 for (i = 0; i < iommu->num_mmu; i++) in rk_iommu_disable_paging()
492 dev_err(iommu->dev, "Disable paging request timed out, status: %#08x\n", in rk_iommu_disable_paging()
493 rk_iommu_read(iommu->bases[i], RK_MMU_STATUS)); in rk_iommu_disable_paging()
498 static int rk_iommu_force_reset(struct rk_iommu *iommu) in rk_iommu_force_reset() argument
504 if (iommu->reset_disabled) in rk_iommu_force_reset()
509 * and verifying that upper 5 (v1) or 7 (v2) nybbles are read back. in rk_iommu_force_reset()
511 for (i = 0; i < iommu->num_mmu; i++) { in rk_iommu_force_reset()
512 dte_addr = rk_ops->pt_address(DTE_ADDR_DUMMY); in rk_iommu_force_reset()
513 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, dte_addr); in rk_iommu_force_reset()
515 if (dte_addr != rk_iommu_read(iommu->bases[i], RK_MMU_DTE_ADDR)) { in rk_iommu_force_reset()
516 dev_err(iommu->dev, "Error during raw reset. MMU_DTE_ADDR is not functioning\n"); in rk_iommu_force_reset()
517 return -EFAULT; in rk_iommu_force_reset()
521 rk_iommu_command(iommu, RK_MMU_CMD_FORCE_RESET); in rk_iommu_force_reset()
523 ret = readx_poll_timeout(rk_iommu_is_reset_done, iommu, val, in rk_iommu_force_reset()
527 dev_err(iommu->dev, "FORCE_RESET command timed out\n"); in rk_iommu_force_reset()
534 static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova) in log_iova() argument
536 void __iomem *base = iommu->bases[index]; in log_iova()
553 mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr); in log_iova()
562 pte_addr_phys = rk_ops->pt_address(dte) + (pte_index * 4); in log_iova()
569 page_addr_phys = rk_ops->pt_address(pte) + page_offset; in log_iova()
573 dev_err(iommu->dev, "iova = %pad: dte_index: %#03x pte_index: %#03x page_offset: %#03x\n", in log_iova()
575 …dev_err(iommu->dev, "mmu_dte_addr: %pa dte@%pa: %#08x valid: %u pte@%pa: %#08x valid: %u page@%pa … in log_iova()
583 struct rk_iommu *iommu = dev_id; in rk_iommu_irq() local
590 err = pm_runtime_get_if_in_use(iommu->dev); in rk_iommu_irq()
594 if (WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks))) in rk_iommu_irq()
597 for (i = 0; i < iommu->num_mmu; i++) { in rk_iommu_irq()
598 int_status = rk_iommu_read(iommu->bases[i], RK_MMU_INT_STATUS); in rk_iommu_irq()
603 iova = rk_iommu_read(iommu->bases[i], RK_MMU_PAGE_FAULT_ADDR); in rk_iommu_irq()
608 status = rk_iommu_read(iommu->bases[i], RK_MMU_STATUS); in rk_iommu_irq()
612 dev_err(iommu->dev, "Page fault at %pad of type %s\n", in rk_iommu_irq()
616 log_iova(iommu, i, iova); in rk_iommu_irq()
623 if (iommu->domain != &rk_identity_domain) in rk_iommu_irq()
624 report_iommu_fault(iommu->domain, iommu->dev, iova, in rk_iommu_irq()
627 dev_err(iommu->dev, "Page fault while iommu not attached to domain?\n"); in rk_iommu_irq()
629 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); in rk_iommu_irq()
630 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_PAGE_FAULT_DONE); in rk_iommu_irq()
634 dev_err(iommu->dev, "BUS_ERROR occurred at %pad\n", &iova); in rk_iommu_irq()
637 dev_err(iommu->dev, "unexpected int_status: %#08x\n", in rk_iommu_irq()
640 rk_iommu_write(iommu->bases[i], RK_MMU_INT_CLEAR, int_status); in rk_iommu_irq()
643 clk_bulk_disable(iommu->num_clocks, iommu->clocks); in rk_iommu_irq()
646 pm_runtime_put(iommu->dev); in rk_iommu_irq()
659 spin_lock_irqsave(&rk_domain->dt_lock, flags); in rk_iommu_iova_to_phys()
661 dte = rk_domain->dt[rk_iova_dte_index(iova)]; in rk_iommu_iova_to_phys()
665 pt_phys = rk_ops->pt_address(dte); in rk_iommu_iova_to_phys()
671 phys = rk_ops->pt_address(pte) + rk_iova_page_offset(iova); in rk_iommu_iova_to_phys()
673 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); in rk_iommu_iova_to_phys()
685 spin_lock_irqsave(&rk_domain->iommus_lock, flags); in rk_iommu_zap_iova()
686 list_for_each(pos, &rk_domain->iommus) { in rk_iommu_zap_iova()
687 struct rk_iommu *iommu; in rk_iommu_zap_iova() local
690 iommu = list_entry(pos, struct rk_iommu, node); in rk_iommu_zap_iova()
693 ret = pm_runtime_get_if_in_use(iommu->dev); in rk_iommu_zap_iova()
697 WARN_ON(clk_bulk_enable(iommu->num_clocks, in rk_iommu_zap_iova()
698 iommu->clocks)); in rk_iommu_zap_iova()
699 rk_iommu_zap_lines(iommu, iova, size); in rk_iommu_zap_iova()
700 clk_bulk_disable(iommu->num_clocks, iommu->clocks); in rk_iommu_zap_iova()
701 pm_runtime_put(iommu->dev); in rk_iommu_zap_iova()
704 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); in rk_iommu_zap_iova()
712 rk_iommu_zap_iova(rk_domain, iova + size - SPAGE_SIZE, in rk_iommu_zap_iova_first_last()
724 assert_spin_locked(&rk_domain->dt_lock); in rk_dte_get_page_table()
727 dte_addr = &rk_domain->dt[dte_index]; in rk_dte_get_page_table()
732 page_table = iommu_alloc_page(GFP_ATOMIC | rk_ops->gfp_flags); in rk_dte_get_page_table()
734 return ERR_PTR(-ENOMEM); in rk_dte_get_page_table()
740 return ERR_PTR(-ENOMEM); in rk_dte_get_page_table()
743 dte = rk_ops->mk_dtentries(pt_dma); in rk_dte_get_page_table()
747 rk_domain->dt_dma + dte_index * sizeof(u32), 1); in rk_dte_get_page_table()
749 pt_phys = rk_ops->pt_address(dte); in rk_dte_get_page_table()
760 assert_spin_locked(&rk_domain->dt_lock); in rk_iommu_unmap_iova()
783 assert_spin_locked(&rk_domain->dt_lock); in rk_iommu_map_iova()
791 pte_addr[pte_count] = rk_ops->mk_ptentries(paddr, prot); in rk_iommu_map_iova()
813 page_phys = rk_ops->pt_address(pte_addr[pte_count]); in rk_iommu_map_iova()
817 return -EADDRINUSE; in rk_iommu_map_iova()
831 spin_lock_irqsave(&rk_domain->dt_lock, flags); in rk_iommu_map()
835 * (1024 4-KiB pages = 4 MiB). in rk_iommu_map()
842 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); in rk_iommu_map()
846 dte_index = rk_domain->dt[rk_iova_dte_index(iova)]; in rk_iommu_map()
850 pte_dma = rk_ops->pt_address(dte_index) + pte_index * sizeof(u32); in rk_iommu_map()
854 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); in rk_iommu_map()
872 spin_lock_irqsave(&rk_domain->dt_lock, flags); in rk_iommu_unmap()
876 * (1024 4-KiB pages = 4 MiB). in rk_iommu_unmap()
881 dte = rk_domain->dt[rk_iova_dte_index(iova)]; in rk_iommu_unmap()
884 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); in rk_iommu_unmap()
888 pt_phys = rk_ops->pt_address(dte); in rk_iommu_unmap()
893 spin_unlock_irqrestore(&rk_domain->dt_lock, flags); in rk_iommu_unmap()
905 return data ? data->iommu : NULL; in rk_iommu_from_dev()
908 /* Must be called with iommu powered on and attached */
909 static void rk_iommu_disable(struct rk_iommu *iommu) in rk_iommu_disable() argument
914 WARN_ON(clk_bulk_enable(iommu->num_clocks, iommu->clocks)); in rk_iommu_disable()
915 rk_iommu_enable_stall(iommu); in rk_iommu_disable()
916 rk_iommu_disable_paging(iommu); in rk_iommu_disable()
917 for (i = 0; i < iommu->num_mmu; i++) { in rk_iommu_disable()
918 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, 0); in rk_iommu_disable()
919 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, 0); in rk_iommu_disable()
921 rk_iommu_disable_stall(iommu); in rk_iommu_disable()
922 clk_bulk_disable(iommu->num_clocks, iommu->clocks); in rk_iommu_disable()
925 /* Must be called with iommu powered on and attached */
926 static int rk_iommu_enable(struct rk_iommu *iommu) in rk_iommu_enable() argument
928 struct iommu_domain *domain = iommu->domain; in rk_iommu_enable()
932 ret = clk_bulk_enable(iommu->num_clocks, iommu->clocks); in rk_iommu_enable()
936 ret = rk_iommu_enable_stall(iommu); in rk_iommu_enable()
940 ret = rk_iommu_force_reset(iommu); in rk_iommu_enable()
944 for (i = 0; i < iommu->num_mmu; i++) { in rk_iommu_enable()
945 rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR, in rk_iommu_enable()
946 rk_ops->mk_dtentries(rk_domain->dt_dma)); in rk_iommu_enable()
947 rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE); in rk_iommu_enable()
948 rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK); in rk_iommu_enable()
951 ret = rk_iommu_enable_paging(iommu); in rk_iommu_enable()
954 rk_iommu_disable_stall(iommu); in rk_iommu_enable()
956 clk_bulk_disable(iommu->num_clocks, iommu->clocks); in rk_iommu_enable()
963 struct rk_iommu *iommu; in rk_iommu_identity_attach() local
969 iommu = rk_iommu_from_dev(dev); in rk_iommu_identity_attach()
970 if (!iommu) in rk_iommu_identity_attach()
971 return -ENODEV; in rk_iommu_identity_attach()
973 rk_domain = to_rk_domain(iommu->domain); in rk_iommu_identity_attach()
975 dev_dbg(dev, "Detaching from iommu domain\n"); in rk_iommu_identity_attach()
977 if (iommu->domain == identity_domain) in rk_iommu_identity_attach()
980 iommu->domain = identity_domain; in rk_iommu_identity_attach()
982 spin_lock_irqsave(&rk_domain->iommus_lock, flags); in rk_iommu_identity_attach()
983 list_del_init(&iommu->node); in rk_iommu_identity_attach()
984 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); in rk_iommu_identity_attach()
986 ret = pm_runtime_get_if_in_use(iommu->dev); in rk_iommu_identity_attach()
989 rk_iommu_disable(iommu); in rk_iommu_identity_attach()
990 pm_runtime_put(iommu->dev); in rk_iommu_identity_attach()
1008 struct rk_iommu *iommu; in rk_iommu_attach_device() local
1015 * Such a device does not belong to an iommu group. in rk_iommu_attach_device()
1017 iommu = rk_iommu_from_dev(dev); in rk_iommu_attach_device()
1018 if (!iommu) in rk_iommu_attach_device()
1021 dev_dbg(dev, "Attaching to iommu domain\n"); in rk_iommu_attach_device()
1023 /* iommu already attached */ in rk_iommu_attach_device()
1024 if (iommu->domain == domain) in rk_iommu_attach_device()
1031 iommu->domain = domain; in rk_iommu_attach_device()
1033 spin_lock_irqsave(&rk_domain->iommus_lock, flags); in rk_iommu_attach_device()
1034 list_add_tail(&iommu->node, &rk_domain->iommus); in rk_iommu_attach_device()
1035 spin_unlock_irqrestore(&rk_domain->iommus_lock, flags); in rk_iommu_attach_device()
1037 ret = pm_runtime_get_if_in_use(iommu->dev); in rk_iommu_attach_device()
1041 ret = rk_iommu_enable(iommu); in rk_iommu_attach_device()
1045 pm_runtime_put(iommu->dev); in rk_iommu_attach_device()
1063 * Each level1 (dt) and level2 (pt) table has 1024 4-byte entries. in rk_iommu_domain_alloc_paging()
1066 rk_domain->dt = iommu_alloc_page(GFP_KERNEL | rk_ops->gfp_flags); in rk_iommu_domain_alloc_paging()
1067 if (!rk_domain->dt) in rk_iommu_domain_alloc_paging()
1070 rk_domain->dt_dma = dma_map_single(dma_dev, rk_domain->dt, in rk_iommu_domain_alloc_paging()
1072 if (dma_mapping_error(dma_dev, rk_domain->dt_dma)) { in rk_iommu_domain_alloc_paging()
1077 spin_lock_init(&rk_domain->iommus_lock); in rk_iommu_domain_alloc_paging()
1078 spin_lock_init(&rk_domain->dt_lock); in rk_iommu_domain_alloc_paging()
1079 INIT_LIST_HEAD(&rk_domain->iommus); in rk_iommu_domain_alloc_paging()
1081 rk_domain->domain.geometry.aperture_start = 0; in rk_iommu_domain_alloc_paging()
1082 rk_domain->domain.geometry.aperture_end = DMA_BIT_MASK(32); in rk_iommu_domain_alloc_paging()
1083 rk_domain->domain.geometry.force_aperture = true; in rk_iommu_domain_alloc_paging()
1085 return &rk_domain->domain; in rk_iommu_domain_alloc_paging()
1088 iommu_free_page(rk_domain->dt); in rk_iommu_domain_alloc_paging()
1100 WARN_ON(!list_empty(&rk_domain->iommus)); in rk_iommu_domain_free()
1103 u32 dte = rk_domain->dt[i]; in rk_iommu_domain_free()
1105 phys_addr_t pt_phys = rk_ops->pt_address(dte); in rk_iommu_domain_free()
1113 dma_unmap_single(dma_dev, rk_domain->dt_dma, in rk_iommu_domain_free()
1115 iommu_free_page(rk_domain->dt); in rk_iommu_domain_free()
1123 struct rk_iommu *iommu; in rk_iommu_probe_device() local
1127 return ERR_PTR(-ENODEV); in rk_iommu_probe_device()
1129 iommu = rk_iommu_from_dev(dev); in rk_iommu_probe_device()
1131 data->link = device_link_add(dev, iommu->dev, in rk_iommu_probe_device()
1134 return &iommu->iommu; in rk_iommu_probe_device()
1141 device_link_del(data->link); in rk_iommu_release_device()
1152 return -ENOMEM; in rk_iommu_of_xlate()
1154 iommu_dev = of_find_device_by_node(args->np); in rk_iommu_of_xlate()
1156 data->iommu = platform_get_drvdata(iommu_dev); in rk_iommu_of_xlate()
1157 data->iommu->domain = &rk_identity_domain; in rk_iommu_of_xlate()
1184 struct device *dev = &pdev->dev; in rk_iommu_probe()
1185 struct rk_iommu *iommu; in rk_iommu_probe() local
1188 int num_res = pdev->num_resources; in rk_iommu_probe()
1191 iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL); in rk_iommu_probe()
1192 if (!iommu) in rk_iommu_probe()
1193 return -ENOMEM; in rk_iommu_probe()
1195 platform_set_drvdata(pdev, iommu); in rk_iommu_probe()
1196 iommu->dev = dev; in rk_iommu_probe()
1197 iommu->num_mmu = 0; in rk_iommu_probe()
1208 return -EINVAL; in rk_iommu_probe()
1210 iommu->bases = devm_kcalloc(dev, num_res, sizeof(*iommu->bases), in rk_iommu_probe()
1212 if (!iommu->bases) in rk_iommu_probe()
1213 return -ENOMEM; in rk_iommu_probe()
1219 iommu->bases[i] = devm_ioremap_resource(&pdev->dev, res); in rk_iommu_probe()
1220 if (IS_ERR(iommu->bases[i])) in rk_iommu_probe()
1222 iommu->num_mmu++; in rk_iommu_probe()
1224 if (iommu->num_mmu == 0) in rk_iommu_probe()
1225 return PTR_ERR(iommu->bases[0]); in rk_iommu_probe()
1227 iommu->num_irq = platform_irq_count(pdev); in rk_iommu_probe()
1228 if (iommu->num_irq < 0) in rk_iommu_probe()
1229 return iommu->num_irq; in rk_iommu_probe()
1231 iommu->reset_disabled = device_property_read_bool(dev, in rk_iommu_probe()
1232 "rockchip,disable-mmu-reset"); in rk_iommu_probe()
1234 iommu->num_clocks = ARRAY_SIZE(rk_iommu_clocks); in rk_iommu_probe()
1235 iommu->clocks = devm_kcalloc(iommu->dev, iommu->num_clocks, in rk_iommu_probe()
1236 sizeof(*iommu->clocks), GFP_KERNEL); in rk_iommu_probe()
1237 if (!iommu->clocks) in rk_iommu_probe()
1238 return -ENOMEM; in rk_iommu_probe()
1240 for (i = 0; i < iommu->num_clocks; ++i) in rk_iommu_probe()
1241 iommu->clocks[i].id = rk_iommu_clocks[i]; in rk_iommu_probe()
1244 * iommu clocks should be present for all new devices and devicetrees in rk_iommu_probe()
1248 err = devm_clk_bulk_get(iommu->dev, iommu->num_clocks, iommu->clocks); in rk_iommu_probe()
1249 if (err == -ENOENT) in rk_iommu_probe()
1250 iommu->num_clocks = 0; in rk_iommu_probe()
1254 err = clk_bulk_prepare(iommu->num_clocks, iommu->clocks); in rk_iommu_probe()
1258 err = iommu_device_sysfs_add(&iommu->iommu, dev, NULL, dev_name(dev)); in rk_iommu_probe()
1262 err = iommu_device_register(&iommu->iommu, &rk_iommu_ops, dev); in rk_iommu_probe()
1267 * Use the first registered IOMMU device for domain to use with DMA in rk_iommu_probe()
1269 * IOMMU device.. in rk_iommu_probe()
1272 dma_dev = &pdev->dev; in rk_iommu_probe()
1276 for (i = 0; i < iommu->num_irq; i++) { in rk_iommu_probe()
1284 err = devm_request_irq(iommu->dev, irq, rk_iommu_irq, in rk_iommu_probe()
1285 IRQF_SHARED, dev_name(dev), iommu); in rk_iommu_probe()
1290 dma_set_mask_and_coherent(dev, rk_ops->dma_bit_mask); in rk_iommu_probe()
1296 iommu_device_sysfs_remove(&iommu->iommu); in rk_iommu_probe()
1298 clk_bulk_unprepare(iommu->num_clocks, iommu->clocks); in rk_iommu_probe()
1304 struct rk_iommu *iommu = platform_get_drvdata(pdev); in rk_iommu_shutdown() local
1307 for (i = 0; i < iommu->num_irq; i++) { in rk_iommu_shutdown()
1310 devm_free_irq(iommu->dev, irq, iommu); in rk_iommu_shutdown()
1313 pm_runtime_force_suspend(&pdev->dev); in rk_iommu_shutdown()
1318 struct rk_iommu *iommu = dev_get_drvdata(dev); in rk_iommu_suspend() local
1320 if (iommu->domain == &rk_identity_domain) in rk_iommu_suspend()
1323 rk_iommu_disable(iommu); in rk_iommu_suspend()
1329 struct rk_iommu *iommu = dev_get_drvdata(dev); in rk_iommu_resume() local
1331 if (iommu->domain == &rk_identity_domain) in rk_iommu_resume()
1334 return rk_iommu_enable(iommu); in rk_iommu_resume()
1360 { .compatible = "rockchip,iommu",
1363 { .compatible = "rockchip,rk3568-iommu",