Lines Matching +full:iommu +full:- +full:v1
1 // SPDX-License-Identifier: GPL-2.0-only
3 * IOMMU API for MTK architected m4u v1 implementations
5 * Copyright (c) 2015-2016 MediaTek Inc.
8 * Based on driver/iommu/mtk_iommu.c
14 #include <linux/dma-mapping.h>
18 #include <linux/iommu.h>
29 #include <asm/dma-iommu.h>
30 #include <dt-bindings/memory/mtk-memory-port.h>
31 #include <dt-bindings/memory/mt2701-larb-port.h>
76 #define MT2701_M4U_TF_LARB(TF) (6 - (((TF) >> 13) & 0x7))
78 /* MTK generation one iommu HW only support 4K size mapping */
104 struct iommu_device iommu; member
123 return component_bind_all(dev, &data->larb_imu); in mtk_iommu_v1_bind()
130 component_unbind_all(dev, &data->larb_imu); in mtk_iommu_v1_unbind()
147 for (i = ARRAY_SIZE(mt2701_m4u_in_larb) - 1; i >= 0; i--) in mt2701_m4u_to_larb()
158 return id - mt2701_m4u_in_larb[larb]; in mt2701_m4u_to_port()
164 data->base + REG_MMU_INV_SEL); in mtk_iommu_v1_tlb_flush_all()
165 writel_relaxed(F_ALL_INVLD, data->base + REG_MMU_INVALIDATE); in mtk_iommu_v1_tlb_flush_all()
176 data->base + REG_MMU_INV_SEL); in mtk_iommu_v1_tlb_flush_range()
178 data->base + REG_MMU_INVLD_START_A); in mtk_iommu_v1_tlb_flush_range()
179 writel_relaxed((iova + size - 1) & F_MMU_FAULT_VA_MSK, in mtk_iommu_v1_tlb_flush_range()
180 data->base + REG_MMU_INVLD_END_A); in mtk_iommu_v1_tlb_flush_range()
181 writel_relaxed(F_MMU_INV_RANGE, data->base + REG_MMU_INVALIDATE); in mtk_iommu_v1_tlb_flush_range()
183 ret = readl_poll_timeout_atomic(data->base + REG_MMU_CPE_DONE, in mtk_iommu_v1_tlb_flush_range()
186 dev_warn(data->dev, in mtk_iommu_v1_tlb_flush_range()
191 writel_relaxed(0, data->base + REG_MMU_CPE_DONE); in mtk_iommu_v1_tlb_flush_range()
197 struct mtk_iommu_v1_domain *dom = data->m4u_dom; in mtk_iommu_v1_isr()
202 int_state = readl_relaxed(data->base + REG_MMU_FAULT_ST); in mtk_iommu_v1_isr()
203 fault_iova = readl_relaxed(data->base + REG_MMU_FAULT_VA); in mtk_iommu_v1_isr()
206 fault_pa = readl_relaxed(data->base + REG_MMU_INVLD_PA); in mtk_iommu_v1_isr()
207 regval = readl_relaxed(data->base + REG_MMU_INT_ID); in mtk_iommu_v1_isr()
212 * MTK v1 iommu HW could not determine whether the fault is read or in mtk_iommu_v1_isr()
215 if (report_iommu_fault(&dom->domain, data->dev, fault_iova, in mtk_iommu_v1_isr()
217 dev_err_ratelimited(data->dev, in mtk_iommu_v1_isr()
223 regval = readl_relaxed(data->base + REG_MMU_INT_CONTROL); in mtk_iommu_v1_isr()
225 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); in mtk_iommu_v1_isr()
240 for (i = 0; i < fwspec->num_ids; ++i) { in mtk_iommu_v1_config()
241 larbid = mt2701_m4u_to_larb(fwspec->ids[i]); in mtk_iommu_v1_config()
242 portid = mt2701_m4u_to_port(fwspec->ids[i]); in mtk_iommu_v1_config()
243 larb_mmu = &data->larb_imu[larbid]; in mtk_iommu_v1_config()
245 dev_dbg(dev, "%s iommu port: %d\n", in mtk_iommu_v1_config()
249 larb_mmu->mmu |= MTK_SMI_MMU_EN(portid); in mtk_iommu_v1_config()
251 larb_mmu->mmu &= ~MTK_SMI_MMU_EN(portid); in mtk_iommu_v1_config()
257 struct mtk_iommu_v1_domain *dom = data->m4u_dom; in mtk_iommu_v1_domain_finalise()
259 spin_lock_init(&dom->pgtlock); in mtk_iommu_v1_domain_finalise()
261 dom->pgt_va = dma_alloc_coherent(data->dev, M2701_IOMMU_PGT_SIZE, in mtk_iommu_v1_domain_finalise()
262 &dom->pgt_pa, GFP_KERNEL); in mtk_iommu_v1_domain_finalise()
263 if (!dom->pgt_va) in mtk_iommu_v1_domain_finalise()
264 return -ENOMEM; in mtk_iommu_v1_domain_finalise()
266 writel(dom->pgt_pa, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_v1_domain_finalise()
268 dom->data = data; in mtk_iommu_v1_domain_finalise()
281 return &dom->domain; in mtk_iommu_v1_domain_alloc_paging()
287 struct mtk_iommu_v1_data *data = dom->data; in mtk_iommu_v1_domain_free()
289 dma_free_coherent(data->dev, M2701_IOMMU_PGT_SIZE, in mtk_iommu_v1_domain_free()
290 dom->pgt_va, dom->pgt_pa); in mtk_iommu_v1_domain_free()
302 mtk_mapping = data->mapping; in mtk_iommu_v1_attach_device()
303 if (mtk_mapping->domain != domain) in mtk_iommu_v1_attach_device()
306 if (!data->m4u_dom) { in mtk_iommu_v1_attach_device()
307 data->m4u_dom = dom; in mtk_iommu_v1_attach_device()
310 data->m4u_dom = NULL; in mtk_iommu_v1_attach_device()
344 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); in mtk_iommu_v1_map()
347 spin_lock_irqsave(&dom->pgtlock, flags); in mtk_iommu_v1_map()
355 spin_unlock_irqrestore(&dom->pgtlock, flags); in mtk_iommu_v1_map()
358 mtk_iommu_v1_tlb_flush_range(dom->data, iova, *mapped); in mtk_iommu_v1_map()
360 return i == pgcount ? 0 : -EEXIST; in mtk_iommu_v1_map()
369 u32 *pgt_base_iova = dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT); in mtk_iommu_v1_unmap()
372 spin_lock_irqsave(&dom->pgtlock, flags); in mtk_iommu_v1_unmap()
374 spin_unlock_irqrestore(&dom->pgtlock, flags); in mtk_iommu_v1_unmap()
376 mtk_iommu_v1_tlb_flush_range(dom->data, iova, size); in mtk_iommu_v1_unmap()
387 spin_lock_irqsave(&dom->pgtlock, flags); in mtk_iommu_v1_iova_to_phys()
388 pa = *(dom->pgt_va + (iova >> MT2701_IOMMU_PAGE_SHIFT)); in mtk_iommu_v1_iova_to_phys()
389 pa = pa & (~(MT2701_IOMMU_PAGE_SIZE - 1)); in mtk_iommu_v1_iova_to_phys()
390 spin_unlock_irqrestore(&dom->pgtlock, flags); in mtk_iommu_v1_iova_to_phys()
398 * MTK generation one iommu HW only support one iommu domain, and all the client
409 if (args->args_count != 1) { in mtk_iommu_v1_create_mapping()
410 dev_err(dev, "invalid #iommu-cells(%d) property for IOMMU\n", in mtk_iommu_v1_create_mapping()
411 args->args_count); in mtk_iommu_v1_create_mapping()
412 return -EINVAL; in mtk_iommu_v1_create_mapping()
415 ret = iommu_fwspec_init(dev, of_fwnode_handle(args->np)); in mtk_iommu_v1_create_mapping()
421 m4updev = of_find_device_by_node(args->np); in mtk_iommu_v1_create_mapping()
423 return -EINVAL; in mtk_iommu_v1_create_mapping()
428 ret = iommu_fwspec_add_ids(dev, args->args, 1); in mtk_iommu_v1_create_mapping()
433 mtk_mapping = data->mapping; in mtk_iommu_v1_create_mapping()
435 /* MTK iommu support 4GB iova address space. */ in mtk_iommu_v1_create_mapping()
440 data->mapping = mtk_mapping; in mtk_iommu_v1_create_mapping()
464 while (!of_parse_phandle_with_args(dev->of_node, "iommus", in mtk_iommu_v1_probe_device()
465 "#iommu-cells", in mtk_iommu_v1_probe_device()
473 /* dev->iommu_fwspec might have changed */ in mtk_iommu_v1_probe_device()
480 /* Link the consumer device with the smi-larb device(supplier) */ in mtk_iommu_v1_probe_device()
481 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); in mtk_iommu_v1_probe_device()
483 return ERR_PTR(-EINVAL); in mtk_iommu_v1_probe_device()
485 for (idx = 1; idx < fwspec->num_ids; idx++) { in mtk_iommu_v1_probe_device()
486 larbidx = mt2701_m4u_to_larb(fwspec->ids[idx]); in mtk_iommu_v1_probe_device()
488 dev_err(dev, "Can only use one larb. Fail@larb%d-%d.\n", in mtk_iommu_v1_probe_device()
490 return ERR_PTR(-EINVAL); in mtk_iommu_v1_probe_device()
494 larbdev = data->larb_imu[larbid].dev; in mtk_iommu_v1_probe_device()
496 return ERR_PTR(-EINVAL); in mtk_iommu_v1_probe_device()
503 return &data->iommu; in mtk_iommu_v1_probe_device()
513 mtk_mapping = data->mapping; in mtk_iommu_v1_probe_finalize()
517 dev_err(dev, "Can't create IOMMU mapping - DMA-OPS will not work\n"); in mtk_iommu_v1_probe_finalize()
528 larbid = mt2701_m4u_to_larb(fwspec->ids[0]); in mtk_iommu_v1_release_device()
529 larbdev = data->larb_imu[larbid].dev; in mtk_iommu_v1_release_device()
538 ret = clk_prepare_enable(data->bclk); in mtk_iommu_v1_hw_init()
540 dev_err(data->dev, "Failed to enable iommu bclk(%d)\n", ret); in mtk_iommu_v1_hw_init()
545 writel_relaxed(regval, data->base + REG_MMU_CTRL_REG); in mtk_iommu_v1_hw_init()
555 writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL); in mtk_iommu_v1_hw_init()
558 writel_relaxed(data->protect_base, in mtk_iommu_v1_hw_init()
559 data->base + REG_MMU_IVRP_PADDR); in mtk_iommu_v1_hw_init()
561 writel_relaxed(F_MMU_DCM_ON, data->base + REG_MMU_DCM); in mtk_iommu_v1_hw_init()
563 if (devm_request_irq(data->dev, data->irq, mtk_iommu_v1_isr, 0, in mtk_iommu_v1_hw_init()
564 dev_name(data->dev), (void *)data)) { in mtk_iommu_v1_hw_init()
565 writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_v1_hw_init()
566 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_hw_init()
567 dev_err(data->dev, "Failed @ IRQ-%d Request\n", data->irq); in mtk_iommu_v1_hw_init()
568 return -ENODEV; in mtk_iommu_v1_hw_init()
593 { .compatible = "mediatek,mt2701-m4u", },
605 struct device *dev = &pdev->dev; in mtk_iommu_v1_probe()
614 return -ENOMEM; in mtk_iommu_v1_probe()
616 data->dev = dev; in mtk_iommu_v1_probe()
622 return -ENOMEM; in mtk_iommu_v1_probe()
623 data->protect_base = ALIGN(virt_to_phys(protect), MTK_PROTECT_PA_ALIGN); in mtk_iommu_v1_probe()
626 data->base = devm_ioremap_resource(dev, res); in mtk_iommu_v1_probe()
627 if (IS_ERR(data->base)) in mtk_iommu_v1_probe()
628 return PTR_ERR(data->base); in mtk_iommu_v1_probe()
630 data->irq = platform_get_irq(pdev, 0); in mtk_iommu_v1_probe()
631 if (data->irq < 0) in mtk_iommu_v1_probe()
632 return data->irq; in mtk_iommu_v1_probe()
634 data->bclk = devm_clk_get(dev, "bclk"); in mtk_iommu_v1_probe()
635 if (IS_ERR(data->bclk)) in mtk_iommu_v1_probe()
636 return PTR_ERR(data->bclk); in mtk_iommu_v1_probe()
638 larb_nr = of_count_phandle_with_args(dev->of_node, in mtk_iommu_v1_probe()
647 larbnode = of_parse_phandle(dev->of_node, "mediatek,larbs", i); in mtk_iommu_v1_probe()
649 return -EINVAL; in mtk_iommu_v1_probe()
659 return -ENODEV; in mtk_iommu_v1_probe()
661 if (!plarbdev->dev.driver) { in mtk_iommu_v1_probe()
663 return -EPROBE_DEFER; in mtk_iommu_v1_probe()
665 data->larb_imu[i].dev = &plarbdev->dev; in mtk_iommu_v1_probe()
677 ret = iommu_device_sysfs_add(&data->iommu, &pdev->dev, NULL, in mtk_iommu_v1_probe()
678 dev_name(&pdev->dev)); in mtk_iommu_v1_probe()
682 ret = iommu_device_register(&data->iommu, &mtk_iommu_v1_ops, dev); in mtk_iommu_v1_probe()
692 iommu_device_unregister(&data->iommu); in mtk_iommu_v1_probe()
694 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_v1_probe()
696 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_probe()
704 iommu_device_sysfs_remove(&data->iommu); in mtk_iommu_v1_remove()
705 iommu_device_unregister(&data->iommu); in mtk_iommu_v1_remove()
707 clk_disable_unprepare(data->bclk); in mtk_iommu_v1_remove()
708 devm_free_irq(&pdev->dev, data->irq, data); in mtk_iommu_v1_remove()
709 component_master_del(&pdev->dev, &mtk_iommu_v1_com_ops); in mtk_iommu_v1_remove()
715 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; in mtk_iommu_v1_suspend()
716 void __iomem *base = data->base; in mtk_iommu_v1_suspend()
718 reg->standard_axi_mode = readl_relaxed(base + in mtk_iommu_v1_suspend()
720 reg->dcm_dis = readl_relaxed(base + REG_MMU_DCM); in mtk_iommu_v1_suspend()
721 reg->ctrl_reg = readl_relaxed(base + REG_MMU_CTRL_REG); in mtk_iommu_v1_suspend()
722 reg->int_control0 = readl_relaxed(base + REG_MMU_INT_CONTROL); in mtk_iommu_v1_suspend()
729 struct mtk_iommu_v1_suspend_reg *reg = &data->reg; in mtk_iommu_v1_resume()
730 void __iomem *base = data->base; in mtk_iommu_v1_resume()
732 writel_relaxed(data->m4u_dom->pgt_pa, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_v1_resume()
733 writel_relaxed(reg->standard_axi_mode, in mtk_iommu_v1_resume()
735 writel_relaxed(reg->dcm_dis, base + REG_MMU_DCM); in mtk_iommu_v1_resume()
736 writel_relaxed(reg->ctrl_reg, base + REG_MMU_CTRL_REG); in mtk_iommu_v1_resume()
737 writel_relaxed(reg->int_control0, base + REG_MMU_INT_CONTROL); in mtk_iommu_v1_resume()
738 writel_relaxed(data->protect_base, base + REG_MMU_IVRP_PADDR); in mtk_iommu_v1_resume()
750 .name = "mtk-iommu-v1",
757 MODULE_DESCRIPTION("IOMMU API for MediaTek M4U v1 implementations");