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/linux/drivers/irqchip/
H A Dirq-ti-sci-intr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Texas Instruments Incorporated - https://www.ti.com/
21 * struct ti_sci_intr_irq_domain - Structure representing a TISCI based
24 * @out_irqs: TISCI resource pointer representing INTR irqs.
26 * @ti_sci_id: TI-SCI device identifier
27 * @type: Specifies the trigger type supported by this Interrupt Router
34 u32 type; member
38 .name = "INTR",
48 * ti_sci_intr_irq_domain_translate() - Retrieve hwirq and type from
53 * @type: IRQ type
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H A Dirq-mips-gic.c6 * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
10 #define pr_fmt(fmt) "irq-mips-gic: " fmt
26 #include <asm/mips-cps.h>
30 #include <dt-bindings/interrupt-controller/mips-gic.h>
44 #define GIC_HWIRQ_TO_LOCAL(x) ((x) - GIC_LOCAL_HWIRQ_BASE)
47 #define GIC_HWIRQ_TO_SHARED(x) ((x) - GIC_SHARED_HWIRQ_BASE)
98 * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers
109 for ((cpu) = __gic_with_next_online_cpu(-1); \
115 * gic_irq_lock_cluster() - Lock redirect block access to IRQ's cluster
150 static void gic_clear_pcpu_masks(unsigned int intr) in gic_clear_pcpu_masks() argument
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
16 The Interrupt Router (INTR) module provides a mechanism to mux M
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
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/linux/drivers/parisc/
H A Diosapic_private.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Copyright (C) 2000,2003 Grant Grundler (grundler at parisc-linux.org)
7 * Copyright (C) 2002 Matthew Wilcox (willy at parisc-linux.org)
15 ** they pack nicely for 64-bit compilation. (ie sizeof(long) == 8)
21 ** -----------------------
24 ** table per cell. N- and L-class consist of a single cell.
28 /* Entry Type 139 identifies an I/O SAPIC interrupt entry */
35 ** Interrupt Type of 0 indicates a vectored interrupt,
47 ** Trigger mode of SAPIC I/O input signals:
49 ** 01 = Edge-triggered
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/linux/drivers/gpu/drm/nouveau/nvkm/engine/
H A Dfalcon.c32 struct nvkm_falcon *falcon = nvkm_falcon(oclass->engine); in nvkm_falcon_oclass_get()
35 while (falcon->func->sclass[c].oclass) { in nvkm_falcon_oclass_get()
37 oclass->base = falcon->func->sclass[index]; in nvkm_falcon_oclass_get()
49 return nvkm_gpuobj_new(object->engine->subdev.device, 256, in nvkm_falcon_cclass_bind()
62 struct nvkm_subdev *subdev = &falcon->engine.subdev; in nvkm_falcon_intr()
63 struct nvkm_device *device = subdev->device; in nvkm_falcon_intr()
64 const u32 base = falcon->addr; in nvkm_falcon_intr()
66 u32 intr = nvkm_rd32(device, base + 0x008) & dest & ~(dest >> 16); in nvkm_falcon_intr() local
73 if (intr & 0x00000040) { in nvkm_falcon_intr()
74 if (falcon->func->intr) { in nvkm_falcon_intr()
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
25 compatible = "ti,am654-timer";
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 ti,timer-pwm;
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H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/timer/
H A Dbase.c29 struct nvkm_subdev *subdev = &wait->tmr->subdev; in nvkm_timer_wait_test()
30 u64 time = nvkm_timer_read(wait->tmr); in nvkm_timer_wait_test()
32 if (wait->reads == 0) { in nvkm_timer_wait_test()
33 wait->time0 = time; in nvkm_timer_wait_test()
34 wait->time1 = time; in nvkm_timer_wait_test()
37 if (wait->time1 == time) { in nvkm_timer_wait_test()
38 if (wait->reads++ == 16) { in nvkm_timer_wait_test()
40 return -ETIMEDOUT; in nvkm_timer_wait_test()
43 wait->time1 = time; in nvkm_timer_wait_test()
44 wait->reads = 1; in nvkm_timer_wait_test()
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/linux/drivers/gpu/drm/xe/
H A Dxe_bo.h1 /* SPDX-License-Identifier: MIT */
26 /* -- */
28 #define XE_BO_FLAG_VRAM(vram) (XE_BO_FLAG_VRAM0 << ((vram)->id))
30 XE_BO_FLAG_VRAM((tile)->mem.vram) : \
53 /* this one is trigger internally only */
63 (XE_BO_FLAG_GGTT0 << (tile)->id)
67 #define XE_PTE_MASK (XE_PAGE_SIZE - 1)
68 #define XE_PDE_SHIFT (XE_PTE_SHIFT - 3)
70 #define XE_PDE_MASK (XE_PDES - 1)
74 #define XE_64K_PTE_MASK (XE_64K_PAGE_SIZE - 1)
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
90 /* Loop limit on how long we wait for auto-negotiation to complete */
172 /* 1000BASE-T Control Register */
176 /* 1000BASE-T Status Register */
190 /* NVM Addressing bits based on type 0=small, 1=large */
239 /* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
262 #define IGC_ICR_RXT0 BIT(7) /* Rx timer intr (ring 0) */
269 #define IGC_ICS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
284 #define IGC_IMS_RXT0 IGC_ICR_RXT0 /* Rx timer intr */
288 #define IGC_QVECTOR_MASK 0x7FFC /* Q-vector mask */
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/linux/arch/powerpc/include/uapi/asm/
H A Dptrace.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
9 * since we can keep non-volatile in the thread_struct
11 * by intr code.
56 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
129 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
132 #define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
138 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
140 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
146 * The transfer totals 34 quadword. Quadwords 0-31 contain the
153 * structures. This also simplifies the implementation of a bi-arch
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/linux/drivers/tty/
H A Dmoxa.c1 // SPDX-License-Identifier: GPL-2.0+
4 * moxa.c -- MOXA Intellio family multiport serial driver.
6 * Copyright (C) 1999-2000 Moxa Technologies (support@moxa.com).
152 * Dual-Ported RAM
171 #define IntrIntr 0x20 /* received INTR code */
175 #define IntrRxTrigger 0x100 /* rx data count reach trigger value */
176 #define IntrTxTrigger 0x200 /* tx data count below trigger value */
205 /* | | +--- RTS flow */
206 /* | +------ TX Xon/Xoff */
207 /* +--------- RX Xon/Xoff */
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/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_svm.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2020-2021 Advanced Micro Devices, Inc.
84 * svm_range_unlink - unlink svm_range from lists and interval tree
90 * Context: The caller must hold svms->lock
94 pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx]\n", prange->svms, in svm_range_unlink()
95 prange, prange->start, prange->last); in svm_range_unlink()
97 if (prange->svm_bo) { in svm_range_unlink()
98 spin_lock(&prange->svm_bo->list_lock); in svm_range_unlink()
99 list_del(&prange->svm_bo_list); in svm_range_unlink()
100 spin_unlock(&prange->svm_bo->list_lock); in svm_range_unlink()
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/linux/arch/x86/kernel/apic/
H A Dio_apic.c1 // SPDX-License-Identifier: GPL-2.0
3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
11 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
25 * - SiS APIC rmw bug:
28 * required to rewrite the index register for a read-modify-write
74 for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
110 /* Saved state during suspend/resume, or while enabling intr-remap. */
142 return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1; in mp_ioapic_pin_count()
147 return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin; in mp_pin_to_gsi()
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/linux/drivers/rtc/
H A Drtc-imxdi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This driver uses the 47-bit 32 kHz counter in the Freescale DryIce block
10 * Since the RTC framework performs API locking via rtc->ops_lock the
41 #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
44 #define DCR_TDCHL (1 << 30) /* Tamper-detect configuration hard lock */
45 #define DCR_TDCSL (1 << 29) /* Tamper-detect configuration soft lock */
46 #define DCR_KSSL (1 << 27) /* Key-select soft lock */
47 #define DCR_MCHL (1 << 20) /* Monotonic-counter hard lock */
48 #define DCR_MCSL (1 << 19) /* Monotonic-counter soft lock */
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/linux/arch/microblaze/boot/dts/
H A Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmxgpu_vi.c281 switch (adev->asic_type) { in xgpu_vi_init_golden_registers()
311 BUG_ON("Doesn't support chip type.\n"); in xgpu_vi_init_golden_registers()
337 timeout -= 1; in xgpu_vi_mailbox_send_ack()
376 return -ENOENT; in xgpu_vi_mailbox_rcv_msg()
381 return -ENOENT; in xgpu_vi_mailbox_rcv_msg()
399 r = -ETIME; in xgpu_vi_poll_ack()
403 timeout -= 5; in xgpu_vi_poll_ack()
419 r = -ETIME; in xgpu_vi_poll_msg()
423 timeout -= 5; in xgpu_vi_poll_msg()
495 DRM_DEBUG("get ack intr and do nothing.\n"); in xgpu_vi_mailbox_ack_irq()
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H A Damdgpu_amdkfd.h54 KFD_MEM_ATT_SHARED, /* Share kgd_mem->bo or another attachment's */
62 enum kfd_mem_attachment_type type; member
114 * Must be last --ends in a flexible-array member.
148 /* MMU-notifier related fields */
249 enum kgd_engine_type type);
284 if ((mmptr) == current->mm) { \
286 } else if (current->flags & PF_KTHREAD) { \
299 ((struct drm_file *)(drm_priv))->driver_priv)->vm)
321 struct amdgpu_device *adev, struct kgd_mem *mem, bool intr);
360 ((adev)->xcp_mgr && (xcp_id) >= 0 ?\
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/linux/drivers/comedi/drivers/
H A Dusbdux.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2003-2014 Bernd Porr, mail@berndporr.me.uk
10 * Devices: [ITL] USB-DUX (usbdux)
26 * wrote the driver for AT-MIO-16d. I used some parts of this
46 * | kernel | registration | usbdux-usb | usbdux-comedi | comedi |
66 * Thanks to Jan-Matthias Braun and Ian to spot the bug and fix it.
97 /* timeout for the USB-transfer in ms */
110 * Size of the input-buffer IN BYTES
122 * Size of the output-buffer in bytes
134 /* Number of in-URBs which receive the data: min=2 */
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/linux/drivers/dma/
H A Dmv_xor.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/dma-mapping.h>
21 #include <linux/platform_data/dma-mv_xor.h>
46 ((chan)->dmadev.dev)
52 struct mv_xor_desc *hw_desc = desc->hw_desc; in mv_desc_init()
54 hw_desc->status = XOR_DESC_DMA_OWNED; in mv_desc_init()
55 hw_desc->phy_next_desc = 0; in mv_desc_init()
56 /* Enable end-of-descriptor interrupts only for DMA_PREP_INTERRUPT */ in mv_desc_init()
57 hw_desc->desc_command = (flags & DMA_PREP_INTERRUPT) ? in mv_desc_init()
59 hw_desc->phy_dest_addr = addr; in mv_desc_init()
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/linux/arch/x86/kvm/
H A Dx86.h1 /* SPDX-License-Identifier: GPL-2.0 */
44 * The host's raw MAXPHYADDR, i.e. the number of non-reserved physical
60 (sizeof(((struct kvm_memslots *)0)->id_hash) * 2 * KVM_MAX_NR_ADDRESS_SPACES)
67 * Assert that "struct kvm_{svm,vmx,tdx}" is an order-0 or order-1 allocation.
68 * Spilling over to an order-2 allocation isn't fundamentally problematic, but
70 * the size is an order-0 allocation when ignoring the memslot hash tables, to
75 BUILD_BUG_ON(get_order(sizeof(struct x) - SIZE_OF_MEMSLOTS_HASHTABLE) && \
106 * KVM's internal, non-ABI indices for synthetic MSRs. The values themselves
140 val -= modifier; in __shrink_ple_window()
154 kvm_x86_ops.nested_ops->leave_nested(vcpu); in kvm_leave_nested()
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/linux/drivers/iommu/intel/
H A Dirq_remapping.c1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
13 #include <linux/irqchip/irq-msi-lib.h>
22 #include <asm/pci-direct.h>
27 #include "../iommu-pages.h"
69 * ->dmar_global_lock
70 * ->irq_2_ir_lock
71 * ->qi->q_lock
72 * ->iommu->register_lock
75 * in single-threaded environment with interrupt disabled, so no need to tabke
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/linux/drivers/net/ethernet/amd/
H A Dariadne.c4 * © Copyright 1995-2003 by Geert Uytterhoeven (geert@linux-m68k.org)
7 * ---------------------------------------------------------------------------
12 * Written 1993-94 by Donald Becker.
14 * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
21 * ---------------------------------------------------------------------------
27 * ---------------------------------------------------------------------------
29 * The Ariadne is a Zorro-II board made by Village Tronic. It contains:
31 * - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
32 * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
34 * - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
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/linux/arch/powerpc/boot/dts/
H A Dmpc8379_rdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
24 #address-cells = <1>;
25 #size-cells = <0>;
30 d-cache-line-size = <32>;
31 i-cache-line-size = <32>;
32 d-cache-size = <32768>;
33 i-cache-size = <32768>;
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