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/linux/fs/befs/
H A Ddatastream.c187 /* Size of indirect block */ in befs_count_blocks()
189 metablocks += ds->indirect.len; in befs_count_blocks()
192 * Double indir block, plus all the indirect blocks it maps. in befs_count_blocks()
193 * In the double-indirect range, all block runs of data are in befs_count_blocks()
195 * how many data block runs are in the double-indirect region, in befs_count_blocks()
196 * and from that we know how many indirect blocks it takes to in befs_count_blocks()
197 * map them. We assume that the indirect blocks are also in befs_count_blocks()
243 * as in the indirect region code).
291 * blockno is in the indirect region of the datastream.
297 * For each block in the indirect run of the datastream, read
[all …]
/linux/Documentation/arch/riscv/
H A Dzicfilp.rst7 Tracking indirect control transfers on RISC-V Linux
11 to enable indirect branch tracking for user mode applications on RISC-V.
28 restriction on such indirect control transfers:
30 - Indirect control transfers must land on a landing pad instruction ``lpad``.
42 This form of indirect control transfer is immutable and doesn't
72 dependencies have been compiled with indirect branch support. Thus
73 it's left to the dynamic loader to enable indirect branch tracking for
79 Per-task indirect branch tracking state can be monitored and
91 ``zicfilp``, then the kernel will enable indirect branch tracking for
94 indirect branch tracking.
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dbranch.json24 …"PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch tha…
27 …"BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that…
30 …"PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts wh…
33 …"BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts whe…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
42 …"PublicDescription": "Indirect branch with predicted address executed. This event counts when any …
45 …"BriefDescription": "Indirect branch with predicted address executed. This event counts when any i…
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A Dbranch.json24 …"PublicDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whi…
27 …"BriefDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whic…
30 …"PublicDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts w…
33 …"BriefDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts wh…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
42 …"PublicDescription": "Indirect branch with predicted address executed.This event counts when any i…
45 …"BriefDescription": "Indirect branch with predicted address executed.This event counts when any in…
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A Dbranch.json30 …"PublicDescription": "Instruction architecturally executed, indirect branch excluding return retir…
33 …"BriefDescription": "Instruction architecturally executed, indirect branch excluding return retire…
48 "PublicDescription": "Instruction architecturally executed, predicted indirect branch",
51 "BriefDescription": "Instruction architecturally executed, predicted indirect branch"
54 "PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",
57 "BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"
72 …"PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding re…
75 …"BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding ret…
78 …"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding…
81 …"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding …
[all …]
/linux/Documentation/admin-guide/hw-vuln/
H A Dspectre.rst62 execution of indirect branches to leak privileged memory.
93 execution of indirect branches :ref:`[3] <spec_ref3>`. The indirect
95 indirect branches can be influenced by an attacker, causing gadget code
102 In Spectre variant 2 attacks, the attacker can steer speculative indirect
104 buffer of a CPU used for predicting indirect branch addresses. Such
105 poisoning could be done by indirect branching into existing code,
106 with the address offset of the indirect branch under the attacker's
109 this could cause privileged code's indirect branch to jump to a gadget
130 steer its indirect branch speculations to gadget code, and measure the
135 Branch History Buffer (BHB) to speculatively steer an indirect branch
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H A Dindirect-target-selection.rst3 Indirect Target Selection (ITS)
8 of indirect branches and RETs located in the lower half of a cacheline.
14 - **eIBRS Guest/Host Isolation**: Indirect branches in KVM/kernel may still be
20 - **Indirect Branch Prediction Barrier (IBPB)**: After an IBPB, indirect
57 As only the indirect branches and RETs that have their last byte of instruction
59 the mitigation is to not allow indirect branches in the lower half.
63 added ITS-safe thunks. These safe thunks consists of indirect branch in the
66 indirect branch.
75 Note, for simplicity, indirect branches in eBPF programs are always replaced
82 thunks. But, RETs significantly outnumber indirect branches, and any benefit
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/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_adminq_cmd.h218 /* command structures and indirect data structures */
222 * - _data for indirect sent data
223 * - _resp for indirect return data (data which is both will use _data)
286 /* Set ARP Proxy command / response (indirect 0x0104) */
298 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
325 /* Manage MAC Address Read Command (indirect 0x0107) */
405 /* Used by many indirect commands that only pass an seid and a buffer in the
417 /* Get Switch Configuration command (indirect 0x0200)
442 /* Get Switch Configuration (indirect 0x0200)
475 /* Get Switch Resource Allocation (indirect 0x0204) */
[all …]
/linux/sound/mips/
H A Dhal2.h13 /* Indirect status register */
28 /* Indirect address register */
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
44 /* blockin which the indirect */
71 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
72 * Indirect Data registers. Write the address to the Indirect Address register
78 * When we write to indirect registers which are larger than one word (16 bit)
79 * we have to fill more than one indirect register before writing. When we read
[all …]
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v4_0_5.c456 * @indirect: indirectly write sram
461 bool indirect) in vcn_v4_0_5_mc_resume_dpg_mode() argument
473 if (!indirect) { in vcn_v4_0_5_mc_resume_dpg_mode()
477 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
481 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
483 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
488 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
490 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
496 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_5_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_2.c377 * @indirect: indirectly write sram
382 bool indirect) in vcn_v5_0_2_mc_resume_dpg_mode() argument
394 if (!indirect) { in vcn_v5_0_2_mc_resume_dpg_mode()
398 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
402 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
404 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
407 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
409 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
411 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
417 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_2_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_0.c420 * @indirect: indirectly write sram
425 bool indirect) in vcn_v5_0_0_mc_resume_dpg_mode() argument
437 if (!indirect) { in vcn_v5_0_0_mc_resume_dpg_mode()
440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
450 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
452 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
458 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v4_0_3.c99 int inst_idx, bool indirect);
541 * @indirect: indirectly write sram
546 bool indirect) in vcn_v4_0_3_mc_resume_dpg_mode() argument
558 if (!indirect) { in vcn_v4_0_3_mc_resume_dpg_mode()
562 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
566 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
568 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
571 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
573 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
575 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_0.c439 bool indirect) in vcn_v2_0_mc_resume_dpg_mode() argument
447 if (!indirect) { in vcn_v2_0_mc_resume_dpg_mode()
450 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
453 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
455 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
458 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
460 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
462 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
468 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
471 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v2_5.c645 bool indirect) in vcn_v2_5_mc_resume_dpg_mode() argument
654 if (!indirect) { in vcn_v2_5_mc_resume_dpg_mode()
657 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
660 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
662 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
665 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
667 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
669 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
675 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
678 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
[all …]
H A Dvcn_v4_0.c505 * @indirect: indirectly write sram
510 bool indirect) in vcn_v4_0_mc_resume_dpg_mode() argument
521 if (!indirect) { in vcn_v4_0_mc_resume_dpg_mode()
524 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
527 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
529 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
532 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
534 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
536 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
542 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
[all …]
H A Dvcn_v5_0_1.c480 * @indirect: indirectly write sram
485 bool indirect) in vcn_v5_0_1_mc_resume_dpg_mode() argument
497 if (!indirect) { in vcn_v5_0_1_mc_resume_dpg_mode()
501 inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
505 inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
507 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
510 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
512 VCN, 0, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
514 VCN, 0, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
520 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_1_mc_resume_dpg_mode()
[all …]
H A Dvcn_v3_0.c573 bool indirect) in vcn_v3_0_mc_resume_dpg_mode() argument
582 if (!indirect) { in vcn_v3_0_mc_resume_dpg_mode()
585 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
588 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
590 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
593 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
595 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
597 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
603 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
606 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
[all …]
H A Djpeg_v5_3_0.c287 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
300 if (indirect) { in jpeg_engine_5_0_0_dpg_clock_gating_mode()
301 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
305 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
307 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
311 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
320 * @indirect: indirectly write sram
324 static int jpeg_v5_3_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_3_0_start_dpg_mode() argument
336 if (indirect) in jpeg_v5_3_0_start_dpg_mode()
340 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); in jpeg_v5_3_0_start_dpg_mode()
[all …]
H A Djpeg_v5_0_0.c304 int inst_idx, uint8_t indirect) in jpeg_engine_5_0_0_dpg_clock_gating_mode() argument
317 if (indirect) { in jpeg_engine_5_0_0_dpg_clock_gating_mode()
318 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
322 ADD_SOC24_JPEG_TO_DPG_SRAM(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
324 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_CTRL, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
328 WREG32_SOC24_JPEG_DPG_MODE(inst_idx, vcnipJPEG_CGC_GATE, data, indirect); in jpeg_engine_5_0_0_dpg_clock_gating_mode()
337 * @indirect: indirectly write sram
341 static int jpeg_v5_0_0_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool indirect) in jpeg_v5_0_0_start_dpg_mode() argument
353 if (indirect) in jpeg_v5_0_0_start_dpg_mode()
357 jpeg_engine_5_0_0_dpg_clock_gating_mode(adev, inst_idx, indirect); in jpeg_v5_0_0_start_dpg_mode()
[all …]
/linux/arch/x86/kernel/
H A Dksysfs.c95 struct setup_indirect *indirect; in get_setup_data_size() local
114 indirect = (struct setup_indirect *)data->data; in get_setup_data_size()
116 if (indirect->type != SETUP_INDIRECT) in get_setup_data_size()
117 *size = indirect->len; in get_setup_data_size()
138 struct setup_indirect *indirect; in type_show() local
162 indirect = (struct setup_indirect *)data->data; in type_show()
164 ret = sprintf(buf, "0x%x\n", indirect->type); in type_show()
179 struct setup_indirect *indirect; in setup_data_data_read() local
203 indirect = (struct setup_indirect *)data->data; in setup_data_data_read()
205 if (indirect->type != SETUP_INDIRECT) { in setup_data_data_read()
[all …]
H A Dkdebugfs.c49 /* Is it direct data or invalid indirect one? */ in setup_data_read()
91 struct setup_indirect *indirect; in create_setup_data_nodes() local
129 indirect = (struct setup_indirect *)data->data; in create_setup_data_nodes()
131 if (indirect->type != SETUP_INDIRECT) { in create_setup_data_nodes()
132 node->paddr = indirect->addr; in create_setup_data_nodes()
133 node->type = indirect->type; in create_setup_data_nodes()
134 node->len = indirect->len; in create_setup_data_nodes()
/linux/arch/m68k/math-emu/
H A Dfp_decode.h29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53 * a0 - will point to source/dest operand for any indirect mode
121 | .long "addr register indirect"
122 | .long "addr register indirect postincrement"
123 | .long "addr register indirect predecrement"
184 | .long "no memory indirect action/reserved","null outer displacement"
196 | test if %pc is the base register for the indirect addr mode
220 | addressing mode: address register indirect
244 | addressing mode: address register indirect with postincrement
263 | addressing mode: address register indirect with predecrement
[all …]
/linux/tools/perf/pmu-events/arch/x86/silvermont/
H A Dpipeline.json8 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
17 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
27 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
37 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
42 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired",
47 …indirect CALL branch instructions retired. Branch prediction predicts the branch target and enabl…
57 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
62 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct…
67 …indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the b…
77 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
[all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen4/
H A Dbranch.json10 …"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a pr…
55 …"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each…
60 "BriefDescription": "Retired indirect branch instructions."
75 "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."

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