| /linux/Documentation/arch/riscv/ |
| H A D | zicfilp.rst | 7 Tracking indirect control transfers on RISC-V Linux
11 to enable indirect branch tracking for user mode applications on RISC-V.
28 restriction on such indirect control transfers:
30 - Indirect control transfers must land on a landing pad instruction ``lpad``.
42 This form of indirect control transfer is immutable and doesn't
72 dependencies have been compiled with indirect branch support. Thus
73 it's left to the dynamic loader to enable indirect branch tracking for
79 Per-task indirect branch tracking state can be monitored and
91 ``zicfilp``, then the kernel will enable indirect branch tracking for
94 indirect branch tracking.
[all …]
|
| /linux/fs/befs/ |
| H A D | datastream.c | 187 /* Size of indirect block */ in befs_count_blocks()
189 metablocks += ds->indirect.len; in befs_count_blocks()
192 * Double indir block, plus all the indirect blocks it maps. in befs_count_blocks()
193 * In the double-indirect range, all block runs of data are in befs_count_blocks()
195 * how many data block runs are in the double-indirect region, in befs_count_blocks()
196 * and from that we know how many indirect blocks it takes to in befs_count_blocks()
197 * map them. We assume that the indirect blocks are also in befs_count_blocks()
243 * as in the indirect region code).
291 * blockno is in the indirect region of the datastream.
297 * For each block in the indirect run of the datastream, read
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/ |
| H A D | branch.json | 24 …"PublicDescription": "Indirect branch mispredicted. This event counts when any indirect branch tha…
27 …"BriefDescription": "Indirect branch mispredicted. This event counts when any indirect branch that…
30 …"PublicDescription": "Indirect branch mispredicted due to address miscompare. This event counts wh…
33 …"BriefDescription": "Indirect branch mispredicted due to address miscompare. This event counts whe…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches that cor…
42 …"PublicDescription": "Indirect branch with predicted address executed. This event counts when any …
45 …"BriefDescription": "Indirect branch with predicted address executed. This event counts when any i…
|
| /linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/ |
| H A D | branch.json | 30 …"PublicDescription": "Instruction architecturally executed, indirect branch excluding return retir…
33 …"BriefDescription": "Instruction architecturally executed, indirect branch excluding return retire…
48 "PublicDescription": "Instruction architecturally executed, predicted indirect branch",
51 "BriefDescription": "Instruction architecturally executed, predicted indirect branch"
54 "PublicDescription": "Instruction architecturally executed, mispredicted indirect branch",
57 "BriefDescription": "Instruction architecturally executed, mispredicted indirect branch"
72 …"PublicDescription": "Instruction architecturally executed, predicted indirect branch excluding re…
75 …"BriefDescription": "Instruction architecturally executed, predicted indirect branch excluding ret…
78 …"PublicDescription": "Instruction architecturally executed, mispredicted indirect branch excluding…
81 …"BriefDescription": "Instruction architecturally executed, mispredicted indirect branch excluding …
[all …]
|
| /linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/ |
| H A D | branch.json | 24 …"PublicDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whi…
27 …"BriefDescription": "Indirect branch mis-predicted.This event counts when any indirect branch whic…
30 …"PublicDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts w…
33 …"BriefDescription": "Indirect branch mis-predicted due to address mis-compare.This event counts wh…
36 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
39 …hen branch prediction is disabled due to the MMU being off. Conditional indirect branches which co…
42 …"PublicDescription": "Indirect branch with predicted address executed.This event counts when any i…
45 …"BriefDescription": "Indirect branch with predicted address executed.This event counts when any in…
|
| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | spectre.rst | 62 execution of indirect branches to leak privileged memory.
93 execution of indirect branches :ref:`[3] <spec_ref3>`. The indirect
95 indirect branches can be influenced by an attacker, causing gadget code
102 In Spectre variant 2 attacks, the attacker can steer speculative indirect
104 buffer of a CPU used for predicting indirect branch addresses. Such
105 poisoning could be done by indirect branching into existing code,
106 with the address offset of the indirect branch under the attacker's
109 this could cause privileged code's indirect branch to jump to a gadget
130 steer its indirect branch speculations to gadget code, and measure the
135 Branch History Buffer (BHB) to speculatively steer an indirect branch
[all …]
|
| H A D | indirect-target-selection.rst | 3 Indirect Target Selection (ITS)
8 of indirect branches and RETs located in the lower half of a cacheline.
14 - **eIBRS Guest/Host Isolation**: Indirect branches in KVM/kernel may still be
20 - **Indirect Branch Prediction Barrier (IBPB)**: After an IBPB, indirect
57 As only the indirect branches and RETs that have their last byte of instruction
59 the mitigation is to not allow indirect branches in the lower half.
63 added ITS-safe thunks. These safe thunks consists of indirect branch in the
66 indirect branch.
75 Note, for simplicity, indirect branches in eBPF programs are always replaced
82 thunks. But, RETs significantly outnumber indirect branches, and any benefit
[all …]
|
| /linux/sound/mips/ |
| H A D | hal2.h | 13 /* Indirect status register */
28 /* Indirect address register */
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
44 /* blockin which the indirect */
71 * The HAL2 has "indirect registers" (idr) which are accessed by writing to the
72 * Indirect Data registers. Write the address to the Indirect Address register
78 * When we write to indirect registers which are larger than one word (16 bit)
79 * we have to fill more than one indirect register before writing. When we read
[all …]
|
| /linux/drivers/net/ethernet/intel/i40e/ |
| H A D | i40e_adminq_cmd.h | 218 /* command structures and indirect data structures */
222 * - _data for indirect sent data
223 * - _resp for indirect return data (data which is both will use _data)
286 /* Set ARP Proxy command / response (indirect 0x0104) */
298 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
325 /* Manage MAC Address Read Command (indirect 0x0107) */
405 /* Used by many indirect commands that only pass an seid and a buffer in the
417 /* Get Switch Configuration command (indirect 0x0200)
442 /* Get Switch Configuration (indirect 0x0200)
475 /* Get Switch Resource Allocation (indirect 0x0204) */
[all …]
|
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vcn_v5_0_0.c | 420 * @indirect: indirectly write sram
425 bool indirect) in vcn_v5_0_0_mc_resume_dpg_mode() argument
437 if (!indirect) { in vcn_v5_0_0_mc_resume_dpg_mode()
440 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
443 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
445 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
448 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
450 VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
452 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
458 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v5_0_0_mc_resume_dpg_mode()
[all …]
|
| H A D | vcn_v2_0.c | 439 bool indirect) in vcn_v2_0_mc_resume_dpg_mode() argument
447 if (!indirect) { in vcn_v2_0_mc_resume_dpg_mode()
450 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
453 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
455 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
458 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
460 UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
462 UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
468 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
471 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
[all …]
|
| H A D | vcn_v3_0.c | 573 bool indirect) in vcn_v3_0_mc_resume_dpg_mode() argument
582 if (!indirect) { in vcn_v3_0_mc_resume_dpg_mode()
585 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
588 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
590 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
593 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
595 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
597 VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
603 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
606 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
[all …]
|
| /linux/arch/x86/kernel/ |
| H A D | ksysfs.c | 95 struct setup_indirect *indirect; in get_setup_data_size() local
114 indirect = (struct setup_indirect *)data->data; in get_setup_data_size()
116 if (indirect->type != SETUP_INDIRECT) in get_setup_data_size()
117 *size = indirect->len; in get_setup_data_size()
138 struct setup_indirect *indirect; in type_show() local
162 indirect = (struct setup_indirect *)data->data; in type_show()
164 ret = sprintf(buf, "0x%x\n", indirect->type); in type_show()
179 struct setup_indirect *indirect; in setup_data_data_read() local
203 indirect = (struct setup_indirect *)data->data; in setup_data_data_read()
205 if (indirect->type != SETUP_INDIRECT) { in setup_data_data_read()
[all …]
|
| H A D | kdebugfs.c | 49 /* Is it direct data or invalid indirect one? */ in setup_data_read()
91 struct setup_indirect *indirect; in create_setup_data_nodes() local
129 indirect = (struct setup_indirect *)data->data; in create_setup_data_nodes()
131 if (indirect->type != SETUP_INDIRECT) { in create_setup_data_nodes()
132 node->paddr = indirect->addr; in create_setup_data_nodes()
133 node->type = indirect->type; in create_setup_data_nodes()
134 node->len = indirect->len; in create_setup_data_nodes()
|
| /linux/arch/m68k/math-emu/ |
| H A D | fp_decode.h | 29 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
53 * a0 - will point to source/dest operand for any indirect mode
121 | .long "addr register indirect"
122 | .long "addr register indirect postincrement"
123 | .long "addr register indirect predecrement"
184 | .long "no memory indirect action/reserved","null outer displacement"
196 | test if %pc is the base register for the indirect addr mode
220 | addressing mode: address register indirect
244 | addressing mode: address register indirect with postincrement
263 | addressing mode: address register indirect with predecrement
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 8 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
17 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
27 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
37 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
42 "BriefDescription": "Counts the number of near indirect CALL branch instructions retired",
47 …indirect CALL branch instructions retired. Branch prediction predicts the branch target and enabl…
57 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
62 …"BriefDescription": "Counts the number of near indirect JMP and near indirect CALL branch instruct…
67 …indirect JMP and near indirect CALL branch instructions retired. Branch prediction predicts the b…
77 …e following branch types: conditional branches, direct calls and jumps, indirect calls and jumps, …
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/amdzen4/ |
| H A D | branch.json | 10 …"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a pr…
55 …"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each…
60 "BriefDescription": "Retired indirect branch instructions."
75 "BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
|
| /linux/include/xen/interface/io/ |
| H A D | blkif.h | 155 * Recognized if "feature-max-indirect-segments" in present in the backend
156 * xenbus info. The "feature-max-indirect-segments" node contains the maximum
160 * maximum number of indirect segments is fixed by the backend, but the
161 * frontend can issue requests with any number of indirect segments as long as
164 * grant references of the pages that are holding the indirect segments.
166 * information about the segments. The number of indirect pages to use is
167 * determined by the number of segments an indirect request contains. Every
168 * indirect page can contain a maximum of
170 * calculate the number of indirect pages to use we have to do
174 * create the "feature-max-indirect-segments" node!
[all …]
|
| /linux/drivers/block/xen-blkback/ |
| H A D | common.h | 50 * This is the maximum number of segments that would be allowed in indirect
111 * The maximum number of indirect segments (and pages) that will
114 * feature-max-indirect-segments entry), so the frontend knows how
115 * many indirect segments the backend supports.
126 struct blkif_x86_32_request_indirect indirect; member
160 uint32_t _pad1; /* offsetof(blkif_..,u.indirect.id)==8 */
167 * The maximum number of indirect segments (and pages) that will
170 * feature-max-indirect-segments entry), so the frontend knows how
171 * many indirect segments the backend supports.
182 struct blkif_x86_64_request_indirect indirect; member
[all …]
|
| H A D | blkback.c | 74 * the use of indirect descriptors, we set it to a value that provides good
927 pages[i]->gref = req->u.indirect.indirect_grefs[i]; in xen_blkbk_parse_indirect()
937 /* Map indirect segments */ in xen_blkbk_parse_indirect()
1104 dst->u.indirect.indirect_op = src->u.indirect.indirect_op; in blkif_get_x86_32_req()
1105 dst->u.indirect.nr_segments = in blkif_get_x86_32_req()
1106 READ_ONCE(src->u.indirect.nr_segments); in blkif_get_x86_32_req()
1107 dst->u.indirect.handle = src->u.indirect.handle; in blkif_get_x86_32_req()
1108 dst->u.indirect.id = src->u.indirect.id; in blkif_get_x86_32_req()
1109 dst->u.indirect.sector_number = src->u.indirect.sector_number; in blkif_get_x86_32_req()
1111 INDIRECT_PAGES(dst->u.indirect.nr_segments)); in blkif_get_x86_32_req()
[all …]
|
| /linux/tools/perf/tests/shell/ |
| H A D | record_lbr.sh | 145 lbr_test "-j ind_call" "any indirect call" 2
146 lbr_test "-j ind_jmp" "any indirect jump" 100
148 lbr_test "-j ind_call,u" "any indirect user call" 100
162 parallel_lbr_test "-j ind_call" "parallel any indirect call" 100 &
164 parallel_lbr_test "-j ind_jmp" "parallel any indirect jump" 100 &
168 parallel_lbr_test "-j ind_call,u" "parallel any indirect user call" 100 &
|
| /linux/drivers/comedi/drivers/tests/ |
| H A D | ni_routes_test.c | 96 /* indirect routes done through muxes */
324 "validate indirect route through rgout0 to TRIGGER_LINE(0)\n"); in test_ni_route_to_register()
326 "validate indirect route through rgout0 to TRIGGER_LINE(1)\n"); in test_ni_route_to_register()
328 "validate indirect route through rgout0 to TRIGGER_LINE(2)\n"); in test_ni_route_to_register()
330 "validate indirect route through rgout0 to TRIGGER_LINE(3)\n"); in test_ni_route_to_register()
334 "validate indirect route through brd0 to TRIGGER_LINE(4)\n"); in test_ni_route_to_register()
337 "validate indirect route through brd0 to TRIGGER_LINE(4)\n"); in test_ni_route_to_register()
340 "validate indirect route through brd1 to TRIGGER_LINE(3)\n"); in test_ni_route_to_register()
343 "validate indirect route through brd1 to TRIGGER_LINE(3)\n"); in test_ni_route_to_register()
346 "validate indirect route through brd2 to TRIGGER_LINE(2)\n"); in test_ni_route_to_register()
[all …]
|
| /linux/arch/arm64/kvm/hyp/ |
| H A D | hyp-entry.S | 216 .macro hyp_ventry indirect, spectrev2
226 .if \indirect != 0
249 .macro generate_vectors indirect, spectrev2
252 hyp_ventry \indirect, \spectrev2
259 generate_vectors indirect = 0, spectrev2 = 1 // HYP_VECTOR_SPECTRE_DIRECT
260 generate_vectors indirect = 1, spectrev2 = 0 // HYP_VECTOR_INDIRECT
261 generate_vectors indirect = 1, spectrev2 = 1 // HYP_VECTOR_SPECTRE_INDIRECT
|
| /linux/tools/testing/selftests/bpf/progs/ |
| H A D | map_ptr_kern.c | 50 static inline int check_bpf_map_ptr(struct bpf_map *indirect, in check_bpf_map_ptr() argument
53 VERIFY(indirect->map_type == direct->map_type); in check_bpf_map_ptr()
54 VERIFY(indirect->key_size == direct->key_size); in check_bpf_map_ptr()
55 VERIFY(indirect->value_size == direct->value_size); in check_bpf_map_ptr()
56 VERIFY(indirect->max_entries == direct->max_entries); in check_bpf_map_ptr()
57 VERIFY(indirect->id == direct->id); in check_bpf_map_ptr()
62 static inline int check(struct bpf_map *indirect, struct bpf_map *direct, in check() argument
65 VERIFY(check_bpf_map_ptr(indirect, direct)); in check()
66 VERIFY(check_bpf_map_fields(indirect, key_size, value_size, in check()
71 static inline int check_default(struct bpf_map *indirect, in check_default() argument
80 check_default_noinline(struct bpf_map * indirect,struct bpf_map * direct) check_default_noinline() argument
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/ivytown/ |
| H A D | pipeline.json | 59 "BriefDescription": "Speculative and retired indirect branches excluding calls and returns",
63 … "PublicDescription": "Speculative and retired indirect branches excluding calls and returns.",
68 "BriefDescription": "Speculative and retired indirect return branches.",
112 … "BriefDescription": "Taken speculative and retired indirect branches excluding calls and returns",
116 …"PublicDescription": "Taken speculative and retired indirect branches excluding calls and returns.…
121 "BriefDescription": "Taken speculative and retired indirect calls",
125 "PublicDescription": "Taken speculative and retired indirect calls.",
130 "BriefDescription": "Taken speculative and retired indirect branches with return mnemonic",
134 … "PublicDescription": "Taken speculative and retired indirect branches with return mnemonic.",
174 "BriefDescription": "Direct and indirect near call instructions retired.",
[all …]
|