xref: /linux/arch/m68k/math-emu/fp_decode.h (revision f26e8817b235d8764363bffcc9cbfc61867371f2)
11da177e4SLinus Torvalds /*
21da177e4SLinus Torvalds  * fp_decode.h
31da177e4SLinus Torvalds  *
41da177e4SLinus Torvalds  * Copyright Roman Zippel, 1997.  All rights reserved.
51da177e4SLinus Torvalds  *
61da177e4SLinus Torvalds  * Redistribution and use in source and binary forms, with or without
71da177e4SLinus Torvalds  * modification, are permitted provided that the following conditions
81da177e4SLinus Torvalds  * are met:
91da177e4SLinus Torvalds  * 1. Redistributions of source code must retain the above copyright
101da177e4SLinus Torvalds  *    notice, and the entire permission notice in its entirety,
111da177e4SLinus Torvalds  *    including the disclaimer of warranties.
121da177e4SLinus Torvalds  * 2. Redistributions in binary form must reproduce the above copyright
131da177e4SLinus Torvalds  *    notice, this list of conditions and the following disclaimer in the
141da177e4SLinus Torvalds  *    documentation and/or other materials provided with the distribution.
151da177e4SLinus Torvalds  * 3. The name of the author may not be used to endorse or promote
161da177e4SLinus Torvalds  *    products derived from this software without specific prior
171da177e4SLinus Torvalds  *    written permission.
181da177e4SLinus Torvalds  *
191da177e4SLinus Torvalds  * ALTERNATIVELY, this product may be distributed under the terms of
201da177e4SLinus Torvalds  * the GNU General Public License, in which case the provisions of the GPL are
211da177e4SLinus Torvalds  * required INSTEAD OF the above restrictions.  (This clause is
221da177e4SLinus Torvalds  * necessary due to a potential bad interaction between the GPL and
231da177e4SLinus Torvalds  * the restrictions contained in a BSD-style copyright.)
241da177e4SLinus Torvalds  *
251da177e4SLinus Torvalds  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
261da177e4SLinus Torvalds  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
271da177e4SLinus Torvalds  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
281da177e4SLinus Torvalds  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
291da177e4SLinus Torvalds  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
301da177e4SLinus Torvalds  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
311da177e4SLinus Torvalds  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
321da177e4SLinus Torvalds  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
331da177e4SLinus Torvalds  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
341da177e4SLinus Torvalds  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
351da177e4SLinus Torvalds  * OF THE POSSIBILITY OF SUCH DAMAGE.
361da177e4SLinus Torvalds  */
371da177e4SLinus Torvalds 
381da177e4SLinus Torvalds #ifndef _FP_DECODE_H
391da177e4SLinus Torvalds #define _FP_DECODE_H
401da177e4SLinus Torvalds 
411da177e4SLinus Torvalds /* These macros do the dirty work of the instr decoding, several variables
421da177e4SLinus Torvalds  * can be defined in the source file to modify the work of these macros,
431da177e4SLinus Torvalds  * currently the following variables are used:
441da177e4SLinus Torvalds  * ...
451da177e4SLinus Torvalds  * The register usage:
461da177e4SLinus Torvalds  * d0 - will contain source operand for data direct mode,
471da177e4SLinus Torvalds  *	otherwise scratch register
481da177e4SLinus Torvalds  * d1 - upper 16bit are reserved for caller
491da177e4SLinus Torvalds  *	lower 16bit may contain further arguments,
501da177e4SLinus Torvalds  *	is destroyed during decoding
511da177e4SLinus Torvalds  * d2 - contains first two instruction words,
521da177e4SLinus Torvalds  *	first word will be used for extension word
531da177e4SLinus Torvalds  * a0 - will point to source/dest operand for any indirect mode
541da177e4SLinus Torvalds  *	otherwise scratch register
551da177e4SLinus Torvalds  * a1 - scratch register
561da177e4SLinus Torvalds  * a2 - base addr to the task structure
571da177e4SLinus Torvalds  *
581da177e4SLinus Torvalds  * the current implementation doesn't check for every disallowed
591da177e4SLinus Torvalds  * addressing mode (e.g. pc relative modes as destination), as long
601da177e4SLinus Torvalds  * as it only means a new addressing mode, which should not appear
611da177e4SLinus Torvalds  * in a program and that doesn't crash the emulation, I think it's
621da177e4SLinus Torvalds  * not a problem to allow these modes.
631da177e4SLinus Torvalds  */
641da177e4SLinus Torvalds 
651da177e4SLinus Torvalds do_fmovem=0
661da177e4SLinus Torvalds do_fmovem_cr=0
671da177e4SLinus Torvalds do_no_pc_mode=0
681da177e4SLinus Torvalds do_fscc=0
691da177e4SLinus Torvalds 
701da177e4SLinus Torvalds | first decoding of the instr type
711da177e4SLinus Torvalds | this separates the conditional instr
721da177e4SLinus Torvalds .macro	fp_decode_cond_instr_type
731da177e4SLinus Torvalds 	bfextu	%d2{#8,#2},%d0
741da177e4SLinus Torvalds 	jmp	([0f:w,%pc,%d0*4])
751da177e4SLinus Torvalds 
761da177e4SLinus Torvalds 	.align	4
771da177e4SLinus Torvalds 0:
781da177e4SLinus Torvalds |	.long	"f<op>","fscc/fdbcc"
791da177e4SLinus Torvalds |	.long	"fbccw","fbccl"
801da177e4SLinus Torvalds .endm
811da177e4SLinus Torvalds 
821da177e4SLinus Torvalds | second decoding of the instr type
831da177e4SLinus Torvalds | this separates most move instr
841da177e4SLinus Torvalds .macro	fp_decode_move_instr_type
851da177e4SLinus Torvalds 	bfextu	%d2{#16,#3},%d0
861da177e4SLinus Torvalds 	jmp	([0f:w,%pc,%d0*4])
871da177e4SLinus Torvalds 
881da177e4SLinus Torvalds 	.align	4
891da177e4SLinus Torvalds 0:
901da177e4SLinus Torvalds |	.long	"f<op> fpx,fpx","invalid instr"
911da177e4SLinus Torvalds |	.long	"f<op> <ea>,fpx","fmove fpx,<ea>"
921da177e4SLinus Torvalds |	.long	"fmovem <ea>,fpcr","fmovem <ea>,fpx"
931da177e4SLinus Torvalds |	.long	"fmovem fpcr,<ea>","fmovem fpx,<ea>"
941da177e4SLinus Torvalds .endm
951da177e4SLinus Torvalds 
961da177e4SLinus Torvalds | extract the source specifier, specifies
971da177e4SLinus Torvalds | either source fp register or data format
981da177e4SLinus Torvalds .macro	fp_decode_sourcespec
991da177e4SLinus Torvalds 	bfextu	%d2{#19,#3},%d0
1001da177e4SLinus Torvalds .endm
1011da177e4SLinus Torvalds 
1021da177e4SLinus Torvalds | decode destination format for fmove reg,ea
1031da177e4SLinus Torvalds .macro	fp_decode_dest_format
1041da177e4SLinus Torvalds 	bfextu	%d2{#19,#3},%d0
1051da177e4SLinus Torvalds .endm
1061da177e4SLinus Torvalds 
1071da177e4SLinus Torvalds | decode source register for fmove reg,ea
1081da177e4SLinus Torvalds .macro	fp_decode_src_reg
1091da177e4SLinus Torvalds 	bfextu	%d2{#22,#3},%d0
1101da177e4SLinus Torvalds .endm
1111da177e4SLinus Torvalds 
1121da177e4SLinus Torvalds | extract the addressing mode
1131da177e4SLinus Torvalds | it depends on the instr which of the modes is valid
1141da177e4SLinus Torvalds .macro	fp_decode_addr_mode
1151da177e4SLinus Torvalds 	bfextu	%d2{#10,#3},%d0
1161da177e4SLinus Torvalds 	jmp	([0f:w,%pc,%d0*4])
1171da177e4SLinus Torvalds 
1181da177e4SLinus Torvalds 	.align	4
1191da177e4SLinus Torvalds 0:
1201da177e4SLinus Torvalds |	.long	"data register direct","addr register direct"
1211da177e4SLinus Torvalds |	.long	"addr register indirect"
1221da177e4SLinus Torvalds |	.long	"addr register indirect postincrement"
1231da177e4SLinus Torvalds |	.long	"addr register indirect predecrement"
1241da177e4SLinus Torvalds |	.long	"addr register + index16"
1251da177e4SLinus Torvalds |	.long	"extension mode1","extension mode2"
1261da177e4SLinus Torvalds .endm
1271da177e4SLinus Torvalds 
1281da177e4SLinus Torvalds | extract the register for the addressing mode
1291da177e4SLinus Torvalds .macro	fp_decode_addr_reg
1301da177e4SLinus Torvalds 	bfextu	%d2{#13,#3},%d0
1311da177e4SLinus Torvalds .endm
1321da177e4SLinus Torvalds 
133*86a8280aSAndrea Gelmini | decode the 8bit displacement from the brief extension word
1341da177e4SLinus Torvalds .macro	fp_decode_disp8
1351da177e4SLinus Torvalds 	move.b	%d2,%d0
1361da177e4SLinus Torvalds 	ext.w	%d0
1371da177e4SLinus Torvalds .endm
1381da177e4SLinus Torvalds 
1391da177e4SLinus Torvalds | decode the index of the brief/full extension word
1401da177e4SLinus Torvalds .macro	fp_decode_index
1411da177e4SLinus Torvalds 	bfextu	%d2{#17,#3},%d0		| get the register nr
1421da177e4SLinus Torvalds 	btst	#15,%d2			| test for data/addr register
1431da177e4SLinus Torvalds 	jne	1\@f
1441da177e4SLinus Torvalds 	printf	PDECODE,"d%d",1,%d0
1451da177e4SLinus Torvalds 	jsr	fp_get_data_reg
1461da177e4SLinus Torvalds 	jra	2\@f
1471da177e4SLinus Torvalds 1\@:	printf	PDECODE,"a%d",1,%d0
1481da177e4SLinus Torvalds 	jsr	fp_get_addr_reg
1491da177e4SLinus Torvalds 	move.l	%a0,%d0
1501da177e4SLinus Torvalds 2\@:
1511da177e4SLinus Torvalds debug	lea	"'l'.w,%a0"
1521da177e4SLinus Torvalds 	btst	#11,%d2			| 16/32 bit size?
1531da177e4SLinus Torvalds 	jne	3\@f
1541da177e4SLinus Torvalds debug	lea	"'w'.w,%a0"
1551da177e4SLinus Torvalds 	ext.l	%d0
1561da177e4SLinus Torvalds 3\@:	printf	PDECODE,":%c",1,%a0
1571da177e4SLinus Torvalds 	move.w	%d2,%d1			| scale factor
1581da177e4SLinus Torvalds 	rol.w	#7,%d1
1591da177e4SLinus Torvalds 	and.w	#3,%d1
1601da177e4SLinus Torvalds debug	move.l	"%d1,-(%sp)"
1611da177e4SLinus Torvalds debug	ext.l	"%d1"
1621da177e4SLinus Torvalds 	printf	PDECODE,":%d",1,%d1
1631da177e4SLinus Torvalds debug	move.l	"(%sp)+,%d1"
1641da177e4SLinus Torvalds 	lsl.l	%d1,%d0
1651da177e4SLinus Torvalds .endm
1661da177e4SLinus Torvalds 
1671da177e4SLinus Torvalds | decode the base displacement size
1681da177e4SLinus Torvalds .macro	fp_decode_basedisp
1691da177e4SLinus Torvalds 	bfextu	%d2{#26,#2},%d0
1701da177e4SLinus Torvalds 	jmp	([0f:w,%pc,%d0*4])
1711da177e4SLinus Torvalds 
1721da177e4SLinus Torvalds 	.align	4
1731da177e4SLinus Torvalds 0:
1741da177e4SLinus Torvalds |	.long	"reserved","null displacement"
1751da177e4SLinus Torvalds |	.long	"word displacement","long displacement"
1761da177e4SLinus Torvalds .endm
1771da177e4SLinus Torvalds 
1781da177e4SLinus Torvalds .macro	fp_decode_outerdisp
1791da177e4SLinus Torvalds 	bfextu	%d2{#30,#2},%d0
1801da177e4SLinus Torvalds 	jmp	([0f:w,%pc,%d0*4])
1811da177e4SLinus Torvalds 
1821da177e4SLinus Torvalds 	.align	4
1831da177e4SLinus Torvalds 0:
1841da177e4SLinus Torvalds |	.long	"no memory indirect action/reserved","null outer displacement"
1851da177e4SLinus Torvalds |	.long	"word outer displacement","long outer displacement"
1861da177e4SLinus Torvalds .endm
1871da177e4SLinus Torvalds 
1881da177e4SLinus Torvalds | get the extension word and test for brief or full extension type
1891da177e4SLinus Torvalds .macro	fp_get_test_extword label
1901da177e4SLinus Torvalds 	fp_get_instr_word %d2,fp_err_ua1
1911da177e4SLinus Torvalds 	btst	#8,%d2
1921da177e4SLinus Torvalds 	jne	\label
1931da177e4SLinus Torvalds .endm
1941da177e4SLinus Torvalds 
1951da177e4SLinus Torvalds 
1961da177e4SLinus Torvalds | test if %pc is the base register for the indirect addr mode
1971da177e4SLinus Torvalds .macro	fp_test_basereg_d16	label
1981da177e4SLinus Torvalds 	btst	#20,%d2
1991da177e4SLinus Torvalds 	jeq	\label
2001da177e4SLinus Torvalds .endm
2011da177e4SLinus Torvalds 
2021da177e4SLinus Torvalds | test if %pc is the base register for one of the extended modes
2031da177e4SLinus Torvalds .macro	fp_test_basereg_ext	label
2041da177e4SLinus Torvalds 	btst	#19,%d2
2051da177e4SLinus Torvalds 	jeq	\label
2061da177e4SLinus Torvalds .endm
2071da177e4SLinus Torvalds 
2081da177e4SLinus Torvalds .macro	fp_test_suppr_index label
2091da177e4SLinus Torvalds 	btst	#6,%d2
2101da177e4SLinus Torvalds 	jne	\label
2111da177e4SLinus Torvalds .endm
2121da177e4SLinus Torvalds 
2131da177e4SLinus Torvalds 
2141da177e4SLinus Torvalds | addressing mode: data register direct
2151da177e4SLinus Torvalds .macro	fp_mode_data_direct
2161da177e4SLinus Torvalds 	fp_decode_addr_reg
2171da177e4SLinus Torvalds 	printf	PDECODE,"d%d",1,%d0
2181da177e4SLinus Torvalds .endm
2191da177e4SLinus Torvalds 
2201da177e4SLinus Torvalds | addressing mode: address register indirect
2211da177e4SLinus Torvalds .macro	fp_mode_addr_indirect
2221da177e4SLinus Torvalds 	fp_decode_addr_reg
2231da177e4SLinus Torvalds 	printf	PDECODE,"(a%d)",1,%d0
2241da177e4SLinus Torvalds 	jsr	fp_get_addr_reg
2251da177e4SLinus Torvalds .endm
2261da177e4SLinus Torvalds 
2271da177e4SLinus Torvalds | adjust stack for byte moves from/to stack
2281da177e4SLinus Torvalds .macro	fp_test_sp_byte_move
2291da177e4SLinus Torvalds 	.if	!do_fmovem
2301da177e4SLinus Torvalds 	.if	do_fscc
2311da177e4SLinus Torvalds 	move.w	#6,%d1
2321da177e4SLinus Torvalds 	.endif
2331da177e4SLinus Torvalds 	cmp.w	#7,%d0
2341da177e4SLinus Torvalds 	jne	1\@f
2351da177e4SLinus Torvalds 	.if	!do_fscc
2361da177e4SLinus Torvalds 	cmp.w	#6,%d1
2371da177e4SLinus Torvalds 	jne	1\@f
2381da177e4SLinus Torvalds 	.endif
2391da177e4SLinus Torvalds 	move.w	#4,%d1
2401da177e4SLinus Torvalds 1\@:
2411da177e4SLinus Torvalds 	.endif
2421da177e4SLinus Torvalds .endm
2431da177e4SLinus Torvalds 
2441da177e4SLinus Torvalds | addressing mode: address register indirect with postincrement
2451da177e4SLinus Torvalds .macro	fp_mode_addr_indirect_postinc
2461da177e4SLinus Torvalds 	fp_decode_addr_reg
2471da177e4SLinus Torvalds 	printf	PDECODE,"(a%d)+",1,%d0
2481da177e4SLinus Torvalds 	fp_test_sp_byte_move
2491da177e4SLinus Torvalds 	jsr	fp_get_addr_reg
2501da177e4SLinus Torvalds 	move.l	%a0,%a1			| save addr
2511da177e4SLinus Torvalds 	.if	do_fmovem
2521da177e4SLinus Torvalds 	lea	(%a0,%d1.w*4),%a0
2531da177e4SLinus Torvalds 	.if	!do_fmovem_cr
2541da177e4SLinus Torvalds 	lea	(%a0,%d1.w*8),%a0
2551da177e4SLinus Torvalds 	.endif
2561da177e4SLinus Torvalds 	.else
2571da177e4SLinus Torvalds 	add.w	(fp_datasize,%d1.w*2),%a0
2581da177e4SLinus Torvalds 	.endif
2591da177e4SLinus Torvalds 	jsr	fp_put_addr_reg
2601da177e4SLinus Torvalds 	move.l	%a1,%a0
2611da177e4SLinus Torvalds .endm
2621da177e4SLinus Torvalds 
2631da177e4SLinus Torvalds | addressing mode: address register indirect with predecrement
2641da177e4SLinus Torvalds .macro	fp_mode_addr_indirect_predec
2651da177e4SLinus Torvalds 	fp_decode_addr_reg
2661da177e4SLinus Torvalds 	printf	PDECODE,"-(a%d)",1,%d0
2671da177e4SLinus Torvalds 	fp_test_sp_byte_move
2681da177e4SLinus Torvalds 	jsr	fp_get_addr_reg
2691da177e4SLinus Torvalds 	.if	do_fmovem
2701da177e4SLinus Torvalds 	.if	!do_fmovem_cr
2711da177e4SLinus Torvalds 	lea	(-12,%a0),%a1		| setup to addr of 1st reg to move
2721da177e4SLinus Torvalds 	neg.w	%d1
2731da177e4SLinus Torvalds 	lea	(%a0,%d1.w*4),%a0
2741da177e4SLinus Torvalds 	add.w	%d1,%d1
2751da177e4SLinus Torvalds 	lea	(%a0,%d1.w*4),%a0
2761da177e4SLinus Torvalds 	jsr	fp_put_addr_reg
2771da177e4SLinus Torvalds 	move.l	%a1,%a0
2781da177e4SLinus Torvalds 	.else
2791da177e4SLinus Torvalds 	neg.w	%d1
2801da177e4SLinus Torvalds 	lea	(%a0,%d1.w*4),%a0
2811da177e4SLinus Torvalds 	jsr	fp_put_addr_reg
2821da177e4SLinus Torvalds 	.endif
2831da177e4SLinus Torvalds 	.else
2841da177e4SLinus Torvalds 	sub.w	(fp_datasize,%d1.w*2),%a0
2851da177e4SLinus Torvalds 	jsr	fp_put_addr_reg
2861da177e4SLinus Torvalds 	.endif
2871da177e4SLinus Torvalds .endm
2881da177e4SLinus Torvalds 
2891da177e4SLinus Torvalds | addressing mode: address register/programm counter indirect
2901da177e4SLinus Torvalds |		   with 16bit displacement
2911da177e4SLinus Torvalds .macro	fp_mode_addr_indirect_disp16
2921da177e4SLinus Torvalds 	.if	!do_no_pc_mode
2931da177e4SLinus Torvalds 	fp_test_basereg_d16 1f
2941da177e4SLinus Torvalds 	printf	PDECODE,"pc"
2951da177e4SLinus Torvalds 	fp_get_pc %a0
2961da177e4SLinus Torvalds 	jra	2f
2971da177e4SLinus Torvalds 	.endif
2981da177e4SLinus Torvalds 1:	fp_decode_addr_reg
2991da177e4SLinus Torvalds 	printf	PDECODE,"a%d",1,%d0
3001da177e4SLinus Torvalds 	jsr	fp_get_addr_reg
3011da177e4SLinus Torvalds 2:	fp_get_instr_word %a1,fp_err_ua1
3021da177e4SLinus Torvalds 	printf	PDECODE,"@(%x)",1,%a1
3031da177e4SLinus Torvalds 	add.l	%a1,%a0
3041da177e4SLinus Torvalds .endm
3051da177e4SLinus Torvalds 
3061da177e4SLinus Torvalds | perform preindex (if I/IS == 0xx and xx != 00)
3071da177e4SLinus Torvalds .macro	fp_do_preindex
3081da177e4SLinus Torvalds 	moveq	#3,%d0
3091da177e4SLinus Torvalds 	and.w	%d2,%d0
3101da177e4SLinus Torvalds 	jeq	1f
3111da177e4SLinus Torvalds 	btst	#2,%d2
3121da177e4SLinus Torvalds 	jne	1f
3131da177e4SLinus Torvalds 	printf	PDECODE,")@("
3141da177e4SLinus Torvalds 	getuser.l (%a1),%a1,fp_err_ua1,%a1
3151da177e4SLinus Torvalds debug	jra	"2f"
3161da177e4SLinus Torvalds 1:	printf	PDECODE,","
3171da177e4SLinus Torvalds 2:
3181da177e4SLinus Torvalds .endm
3191da177e4SLinus Torvalds 
3201da177e4SLinus Torvalds | perform postindex (if I/IS == 1xx)
3211da177e4SLinus Torvalds .macro	fp_do_postindex
3221da177e4SLinus Torvalds 	btst	#2,%d2
3231da177e4SLinus Torvalds 	jeq	1f
3241da177e4SLinus Torvalds 	printf	PDECODE,")@("
3251da177e4SLinus Torvalds 	getuser.l (%a1),%a1,fp_err_ua1,%a1
3261da177e4SLinus Torvalds debug	jra	"2f"
3271da177e4SLinus Torvalds 1:	printf	PDECODE,","
3281da177e4SLinus Torvalds 2:
3291da177e4SLinus Torvalds .endm
3301da177e4SLinus Torvalds 
3311da177e4SLinus Torvalds | all other indirect addressing modes will finally end up here
3321da177e4SLinus Torvalds .macro	fp_mode_addr_indirect_extmode0
3331da177e4SLinus Torvalds 	.if	!do_no_pc_mode
3341da177e4SLinus Torvalds 	fp_test_basereg_ext 1f
3351da177e4SLinus Torvalds 	printf	PDECODE,"pc"
3361da177e4SLinus Torvalds 	fp_get_pc %a0
3371da177e4SLinus Torvalds 	jra	2f
3381da177e4SLinus Torvalds 	.endif
3391da177e4SLinus Torvalds 1:	fp_decode_addr_reg
3401da177e4SLinus Torvalds 	printf	PDECODE,"a%d",1,%d0
3411da177e4SLinus Torvalds 	jsr	fp_get_addr_reg
3421da177e4SLinus Torvalds 2:	move.l	%a0,%a1
3431da177e4SLinus Torvalds 	swap	%d2
3441da177e4SLinus Torvalds 	fp_get_test_extword 3f
3451da177e4SLinus Torvalds 	| addressing mode: address register/programm counter indirect
3461da177e4SLinus Torvalds 	|		   with index and 8bit displacement
3471da177e4SLinus Torvalds 	fp_decode_disp8
3481da177e4SLinus Torvalds debug	ext.l	"%d0"
3491da177e4SLinus Torvalds 	printf	PDECODE,"@(%x,",1,%d0
3501da177e4SLinus Torvalds 	add.w	%d0,%a1
3511da177e4SLinus Torvalds 	fp_decode_index
3521da177e4SLinus Torvalds 	add.l	%d0,%a1
3531da177e4SLinus Torvalds 	printf	PDECODE,")"
3541da177e4SLinus Torvalds 	jra	9f
3551da177e4SLinus Torvalds 3:	| addressing mode: address register/programm counter memory indirect
3561da177e4SLinus Torvalds 	|		   with base and/or outer displacement
3571da177e4SLinus Torvalds 	btst	#7,%d2			| base register suppressed?
3581da177e4SLinus Torvalds 	jeq	1f
3591da177e4SLinus Torvalds 	printf	PDECODE,"!"
3601da177e4SLinus Torvalds 	sub.l	%a1,%a1
3611da177e4SLinus Torvalds 1:	printf	PDECODE,"@("
3621da177e4SLinus Torvalds 	fp_decode_basedisp
3631da177e4SLinus Torvalds 
3641da177e4SLinus Torvalds 	.long	fp_ill,1f
3651da177e4SLinus Torvalds 	.long	2f,3f
3661da177e4SLinus Torvalds 
3671da177e4SLinus Torvalds #ifdef FPU_EMU_DEBUG
3681da177e4SLinus Torvalds 1:	printf	PDECODE,"0"		| null base displacement
3691da177e4SLinus Torvalds 	jra	1f
3701da177e4SLinus Torvalds #endif
3711da177e4SLinus Torvalds 2:	fp_get_instr_word %a0,fp_err_ua1 | 16bit base displacement
3721da177e4SLinus Torvalds 	printf	PDECODE,"%x:w",1,%a0
3731da177e4SLinus Torvalds 	jra	4f
3741da177e4SLinus Torvalds 3:	fp_get_instr_long %a0,fp_err_ua1 | 32bit base displacement
3751da177e4SLinus Torvalds 	printf	PDECODE,"%x:l",1,%a0
3761da177e4SLinus Torvalds 4:	add.l	%a0,%a1
3771da177e4SLinus Torvalds 1:
3781da177e4SLinus Torvalds 	fp_do_postindex
3791da177e4SLinus Torvalds 	fp_test_suppr_index 1f
3801da177e4SLinus Torvalds 	fp_decode_index
3811da177e4SLinus Torvalds 	add.l	%d0,%a1
3821da177e4SLinus Torvalds 1:	fp_do_preindex
3831da177e4SLinus Torvalds 
3841da177e4SLinus Torvalds 	fp_decode_outerdisp
3851da177e4SLinus Torvalds 
3861da177e4SLinus Torvalds 	.long	5f,1f
3871da177e4SLinus Torvalds 	.long	2f,3f
3881da177e4SLinus Torvalds 
3891da177e4SLinus Torvalds #ifdef FPU_EMU_DEBUG
3901da177e4SLinus Torvalds 1:	printf	PDECODE,"0"		| null outer displacement
3911da177e4SLinus Torvalds 	jra	1f
3921da177e4SLinus Torvalds #endif
3931da177e4SLinus Torvalds 2:	fp_get_instr_word %a0,fp_err_ua1 | 16bit outer displacement
3941da177e4SLinus Torvalds 	printf	PDECODE,"%x:w",1,%a0
3951da177e4SLinus Torvalds 	jra	4f
3961da177e4SLinus Torvalds 3:	fp_get_instr_long %a0,fp_err_ua1 | 32bit outer displacement
3971da177e4SLinus Torvalds 	printf	PDECODE,"%x:l",1,%a0
3981da177e4SLinus Torvalds 4:	add.l	%a0,%a1
3991da177e4SLinus Torvalds 1:
4001da177e4SLinus Torvalds 5:	printf	PDECODE,")"
4011da177e4SLinus Torvalds 9:	move.l	%a1,%a0
4021da177e4SLinus Torvalds 	swap	%d2
4031da177e4SLinus Torvalds .endm
4041da177e4SLinus Torvalds 
4051da177e4SLinus Torvalds | get the absolute short address from user space
4061da177e4SLinus Torvalds .macro	fp_mode_abs_short
4071da177e4SLinus Torvalds 	fp_get_instr_word %a0,fp_err_ua1
4081da177e4SLinus Torvalds 	printf	PDECODE,"%x.w",1,%a0
4091da177e4SLinus Torvalds .endm
4101da177e4SLinus Torvalds 
4111da177e4SLinus Torvalds | get the absolute long address from user space
4121da177e4SLinus Torvalds .macro	fp_mode_abs_long
4131da177e4SLinus Torvalds 	fp_get_instr_long %a0,fp_err_ua1
4141da177e4SLinus Torvalds 	printf	PDECODE,"%x.l",1,%a0
4151da177e4SLinus Torvalds .endm
4161da177e4SLinus Torvalds 
4171da177e4SLinus Torvalds #endif /* _FP_DECODE_H */
418