505  * @indirect: indirectly write sram
510 					bool indirect)  in vcn_v4_0_mc_resume_dpg_mode()  argument
521 		if (!indirect) {  in vcn_v4_0_mc_resume_dpg_mode()
524 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
527 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
529 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
532 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
534 				VCN, inst_idx, regUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
536 				VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
542 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
545 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
549 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
552 	if (!indirect)  in vcn_v4_0_mc_resume_dpg_mode()
554 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
557 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
560 	if (!indirect) {  in vcn_v4_0_mc_resume_dpg_mode()
563 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
566 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
568 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
571 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
573 			VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
575 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
578 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
583 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
586 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
588 			VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
590 			VCN, inst_idx, regUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
595 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
598 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
600 			VCN, inst_idx, regUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
603 			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_vcn4_fw_shared)), 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
608 			adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v4_0_mc_resume_dpg_mode()
850  * @indirect: indirectly write sram
856 						   uint8_t indirect)  in vcn_v4_0_disable_clock_gating_dpg_mode()  argument
889 		VCN, inst_idx, regUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
893 		VCN, inst_idx, regUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
897 		VCN, inst_idx, regUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
901 		VCN, inst_idx, regUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v4_0_disable_clock_gating_dpg_mode()
965 				bool indirect)  in vcn_v4_0_enable_ras()  argument
980 			      tmp, 0, indirect);  in vcn_v4_0_enable_ras()
985 			      tmp, 0, indirect);  in vcn_v4_0_enable_ras()
992  * @indirect: indirectly write sram
996 static int vcn_v4_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)  in vcn_v4_0_start_dpg_mode()  argument
1014 	if (indirect)  in vcn_v4_0_start_dpg_mode()
1018 	vcn_v4_0_disable_clock_gating_dpg_mode(vinst, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1024 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1028 		VCN, inst_idx, regUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1040 		VCN, inst_idx, regUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1044 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1051 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
1058 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
1064 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v4_0_start_dpg_mode()
1066 	vcn_v4_0_mc_resume_dpg_mode(vinst, indirect);  in vcn_v4_0_start_dpg_mode()
1071 		VCN, inst_idx, regUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1076 		VCN, inst_idx, regUVD_LMI_CTRL2), tmp, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1078 	vcn_v4_0_enable_ras(vinst, indirect);  in vcn_v4_0_start_dpg_mode()
1083 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v4_0_start_dpg_mode()
1086 	if (indirect) {  in vcn_v4_0_start_dpg_mode()