573 					bool indirect)  in vcn_v3_0_mc_resume_dpg_mode()  argument
582 		if (!indirect) {  in vcn_v3_0_mc_resume_dpg_mode()
585 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
588 				(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
590 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
593 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
595 				VCN, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
597 				VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
603 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
606 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
610 			AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
613 	if (!indirect)  in vcn_v3_0_mc_resume_dpg_mode()
615 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
618 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
621 	if (!indirect) {  in vcn_v3_0_mc_resume_dpg_mode()
624 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
627 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
629 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
632 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
634 			VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
636 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
639 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
644 			lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
647 			upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
649 			VCN, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
651 			VCN, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
656 			lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
659 			upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
661 			VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
664 			AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
668 		UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);  in vcn_v3_0_mc_resume_dpg_mode()
910 					   uint8_t indirect)  in vcn_v3_0_clock_gating_dpg_mode()  argument
944 		VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
948 		VCN, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
952 		VCN, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
956 		VCN, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);  in vcn_v3_0_clock_gating_dpg_mode()
1028 static int vcn_v3_0_start_dpg_mode(struct amdgpu_vcn_inst *vinst, bool indirect)  in vcn_v3_0_start_dpg_mode()  argument
1046 	if (indirect)  in vcn_v3_0_start_dpg_mode()
1050 	vcn_v3_0_clock_gating_dpg_mode(vinst, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1057 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1061 		VCN, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1073 		VCN, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1077 		0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1084 		 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);  in vcn_v3_0_start_dpg_mode()
1091 		 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);  in vcn_v3_0_start_dpg_mode()
1097 		 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);  in vcn_v3_0_start_dpg_mode()
1099 	vcn_v3_0_mc_resume_dpg_mode(vinst, indirect);  in vcn_v3_0_start_dpg_mode()
1102 		VCN, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1104 		VCN, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1108 		VCN, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1112 		VCN, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1117 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1122 		UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1126 		VCN, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);  in vcn_v3_0_start_dpg_mode()
1128 	if (indirect) {  in vcn_v3_0_start_dpg_mode()