Home
last modified time | relevance | path

Searched +full:imx8mp +full:- +full:reset (Results 1 – 25 of 50) sorted by relevance

12

/linux/Documentation/devicetree/bindings/dsp/
H A Dfsl,dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Daniel Baluta <daniel.baluta@nxp.com>
11 - Shengjiu Wang <shengjiu.wang@nxp.com>
15 advanced pre- and post- audio processing.
20 - fsl,imx8qxp-dsp
21 - fsl,imx8qm-dsp
22 - fsl,imx8mp-dsp
23 - fsl,imx8ulp-dsp
[all …]
/linux/drivers/phy/freescale/
H A Dphy-fsl-imx8m-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
18 #include <linux/reset.h>
20 #include <dt-bindings/phy/phy-imx8-pcie.h>
51 IMX8MP, enumerator
65 struct reset_control *reset; member
79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on()
80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on()
82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on()
84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on()
[all …]
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mp-dhcom-pdk2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * DHCOM iMX8MP variant:
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK2 PCB number: 516-400 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som",
[all …]
H A Dimx8mp-skov-revb-mi1010ait-1cp1.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "imx8mp-skov-reva.dtsi"
8 model = "SKOV IMX8MP CPU revB - MI1010AIT-1CP1";
9 compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", "fsl,imx8mp";
12 compatible = "multi-inno,mi1010ait-1cp";
14 power-supply = <&reg_tft_vcom>;
18 remote-endpoint = <&ldb_lvds_ch0>;
29 clock-frequency = <100000>;
33 compatible = "edt,edt-ft5406";
[all …]
H A Dimx8mp-skov-revc-tian-g07017.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "imx8mp-skov-reva.dtsi"
8 model = "SKOV IMX8MP CPU revC - TIAN G07017";
9 compatible = "skov,imx8mp-skov-revc-tian-g07017", "fsl,imx8mp";
12 compatible = "topland,tian-g07017-01";
14 power-supply = <&reg_tft_vcom>;
18 remote-endpoint = <&ldb_lvds_ch0>;
29 clock-frequency = <100000>;
33 compatible = "edt,edt-ft5506";
[all …]
H A Dimx8mp-dhcom-pdk3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * DHCOM iMX8MP variant:
6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2
7 * DHCOM PCB number: 660-100 or newer
8 * PDK3 PCB number: 669-100 or newer
11 /dts-v1/;
13 #include <dt-bindings/leds/common.h>
14 #include <dt-bindings/phy/phy-imx8-pcie.h>
15 #include "imx8mp-dhcom-som.dtsi"
19 compatible = "dh,imx8mp-dhcom-pdk3", "dh,imx8mp-dhcom-som",
[all …]
H A Dimx8mp-skov-revc-bd500.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 /dts-v1/;
5 #include "imx8mp-skov-reva.dtsi"
8 model = "SKOV IMX8MP CPU revC - bd500";
9 compatible = "skov,imx8mp-skov-revc-bd500", "fsl,imx8mp";
12 led_system_red: led-3 {
17 default-state = "off";
20 led_system_green: led-4 {
24 default-state = "on";
27 led_lan1_red: led-5 {
[all …]
H A Dimx8mp-nitrogen-enc-carrier-board.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-nitrogen-som.dtsi"
13 compatible = "boundary,imx8mp-nitrogen-enc-carrier-board",
14 "boundary,imx8mp-nitrogen-som", "fsl,imx8mp";
17 stdout-path = &uart2;
21 compatible = "usb-c-connector";
22 data-role = "dual";
23 label = "USB-C";
26 #address-cells = <1>;
[all …]
H A Dimx8mp-debix-som-a-bmb-08.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include "imx8mp-debix-som-a.dtsi"
12 model = "Polyhex i.MX8MPlus Debix SOM A on BMB-08";
13 compatible = "polyhex,imx8mp-debix-som-a-bmb-08", "polyhex,imx8mp-debix-som-a",
14 "fsl,imx8mp";
22 stdout-path = &uart2;
25 reg_baseboard_vdd3v3: regulator-baseboard-vdd3v3 {
26 compatible = "regulator-fixed";
27 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8mp-debix-model-a.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/usb/pd.h>
13 #include "imx8mp.dtsi"
17 compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
20 stdout-path = &uart2;
23 hdmi-connector {
24 compatible = "hdmi-connector";
[all …]
H A Dimx8mp-tx8p-ml81-moduline-display-106-av101hdt-a10.dtso1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #include <dt-bindings/clock/imx8mp-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
10 #include "imx8mp-pinfunc.h"
12 /dts-v1/;
16 model = "GOcontroll Moduline Display with BOE av101hdt-a10 display";
19 compatible = "boe,av101hdt-a10";
20 enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
21 pinctrl-0 = <&pinctrl_panel>;
22 pinctrl-names = "default";
[all …]
H A Dimx8mp-libra-rdk-fpsc.dts1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/leds/leds-pca9532.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/pwm/pwm.h>
11 #include "imx8mp-phycore-fpsc.dtsi"
14 compatible = "phytec,imx8mp-libra-rdk-fpsc",
15 "phytec,imx8mp-phycore-fpsc", "fsl,imx8mp";
19 compatible = "pwm-backlight";
20 pinctrl-0 = <&pinctrl_lvds0>;
[all …]
H A Dimx8mp-debix-som-a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "imx8mp.dtsi"
9 #include <dt-bindings/leds/common.h>
13 compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";
15 reg_usdhc2_vmmc: regulator-usdhc2 {
16 compatible = "regulator-fixed";
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
19 regulator-name = "VSD_3V3";
20 regulator-min-microvolt = <3300000>;
[all …]
H A Dimx8mp-beacon-kit.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/usb/pd.h>
9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include "imx8mp.dtsi"
11 #include "imx8mp-beacon-som.dtsi"
15 compatible = "beacon,imx8mp-beacon-kit", "fsl,imx8mp";
23 stdout-path = &uart2;
26 clk_xtal25: clock-xtal25 {
27 compatible = "fixed-clock";
[all …]
H A Dimx8mp-phycore-som.dtsi1 // SPDX-License-Identifier: GPL-2.0
7 #include <dt-bindings/net/ti-dp83867.h>
8 #include "imx8mp.dtsi"
11 model = "PHYTEC phyCORE-i.MX8MP";
12 compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
24 reg_vdd_io: regulator-vdd-io {
25 compatible = "regulator-fixed";
26 regulator-always-on;
27 regulator-boot-on;
28 regulator-max-microvolt = <3300000>;
[all …]
H A Dimx8mp-tqma8mpql.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright 2021-2025 TQ-Systems GmbH <linux@ew.tq-group.com>,
4 * D-82229 Seefeld, Germany.
8 #include "imx8mp.dtsi"
11 model = "TQ-Systems i.MX8MPlus TQMa8MPxL";
12 compatible = "tq,imx8mp-tqma8mpql", "fsl,imx8mp";
19 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
20 compatible = "regulator-gpio";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_reg_usdhc2_vqmmc>;
[all …]
/linux/Documentation/devicetree/bindings/reset/
H A Dfsl,imx7-src.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/fsl,imx7-src.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX7 System Reset Controller
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
13 The system reset controller can be used to reset various set of
14 peripherals. Device nodes that need access to reset lines should
15 specify them as a reset phandle in their corresponding node as
16 specified in reset.txt.
[all …]
/linux/Documentation/devicetree/bindings/power/
H A Dfsl,imx-gpcv2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/fsl,imx-gpcv2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrey Smirnov <andrew.smirnov@gmail.com>
18 Documentation/devicetree/bindings/power/power-domain.yaml, which are
21 IP cores belonging to a power domain should contain a 'power-domains'
27 - fsl,imx7d-gpc
28 - fsl,imx8mn-gpc
29 - fsl,imx8mq-gpc
[all …]
/linux/sound/soc/sof/imx/
H A Dimx8.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
3 // Copyright 2019-2025 NXP
9 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <linux/arm-smccc.h>
14 #include <linux/reset
[all...]
/linux/Documentation/devicetree/bindings/phy/
H A Dfsl,imx8-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Zhu <hongxing.zhu@nxp.com>
13 "#phy-cells":
18 - fsl,imx8mm-pcie-phy
19 - fsl,imx8mp-pcie-phy
27 clock-names:
29 - const: ref
[all …]
/linux/Documentation/devicetree/bindings/watchdog/
H A Dfsl-imx-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
17 - const: fsl,imx21-wdt
18 - items:
19 - enum:
[all …]
/linux/Documentation/devicetree/bindings/remoteproc/
H A Dfsl,imx-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Co-Processor
10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
13 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx6sx-cm4
19 - fsl,imx7d-cm4
20 - fsl,imx7ulp-cm4
[all …]
/linux/drivers/gpu/drm/bridge/imx/
H A Dimx8mp-hdmi-tx.c1 // SPDX-License-Identifier: GPL-2.0+
28 if (mode->clock < 13500) in imx8mp_hdmi_mode_valid()
31 if (mode->clock > 297000) in imx8mp_hdmi_mode_valid()
34 round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000); in imx8mp_hdmi_mode_valid()
35 /* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate in imx8mp_hdmi_mode_valid()
39 * 0.5% = 5/1000 tolerance (mode->clock is 1/1000) in imx8mp_hdmi_mode_valid()
41 if (abs(round_rate - mode->clock * 1000) > mode->clock * 5) in imx8mp_hdmi_mode_valid()
44 /* We don't support double-clocked and Interlaced modes */ in imx8mp_hdmi_mode_valid()
45 if ((mode->flags & DRM_MODE_FLAG_DBLCLK) || in imx8mp_hdmi_mode_valid()
46 (mode->flags & DRM_MODE_FLAG_INTERLACE)) in imx8mp_hdmi_mode_valid()
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dtoradex,smarc-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/toradex,smarc-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
11 - Francesco Dolcini <francesco.dolcini@toradex.com>
15 primarily to manage power and reset functionalities.
18 - Reads the SMARC POWER_BTN# and RESET_IN# signals and controls the PMIC accordingly.
19 - Controls the SoC boot mode signals based on the SMARC BOOT_SEL# and FORCE_RECOV# inputs.
20 - Manages the CARRIER_STDBY# signal in response to relevant SoC signals.
[all …]
/linux/drivers/reset/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
[all …]

12