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Searched +full:imx7ulp +full:- +full:scg1 (Results 1 – 9 of 9) sorted by relevance

/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7ulp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
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H A Dimx7ulp-com.dts1 // SPDX-License-Identifier: GPL-2.0
5 /dts-v1/;
7 #include "imx7ulp.dtsi"
8 #include <dt-bindings/input/input.h>
12 compatible = "ea,imx7ulp-com", "fsl,imx7ulp";
15 stdout-path = &lpuart4;
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_lpuart4>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_usbotg1_id>;
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H A Dimx7ulp-evk.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 /dts-v1/;
10 #include "imx7ulp.dtsi"
14 compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp";
17 stdout-path = &lpuart4;
26 compatible = "pwm-backlight";
28 brightness-levels = <0 20 25 30 35 40 100>;
29 default-brightness-level = <6>;
33 reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
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/linux/Documentation/devicetree/bindings/clock/
H A Dimx7ulp-pcc-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - A.s. Dong <aisheng.dong@nxp.com>
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
34 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
40 - fsl,imx7ulp-pcc2
41 - fsl,imx7ulp-pcc3
46 '#clock-cells':
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H A Dimx7ulp-scg-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - A.s. Dong <aisheng.dong@nxp.com>
24 A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
37 See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
42 const: fsl,imx7ulp-scg1
47 '#clock-cells':
52 - description: rtc osc
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/linux/Documentation/devicetree/bindings/watchdog/
H A Dfsl-imx7ulp-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/fsl-imx7ulp-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
15 - $ref: watchdog.yaml#
20 - const: fsl,imx7ulp-wdt
21 - items:
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/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
26 - const: fsl,imx7ulp-tpm
36 - description: SoC TPM ipg clock
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/linux/Documentation/devicetree/bindings/pwm/
H A Dimx-tpm-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-tpm-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Sascha Hauer <s.hauer@pengutronix.de>
12 - Fabio Estevam <festevam@gmail.com>
19 - $ref: pwm.yaml#
22 "#pwm-cells":
27 - fsl,imx7ulp-pwm
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/linux/drivers/clk/imx/
H A Dclk-imx7ulp.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <dt-bindings/clock/imx7ulp-clock.h>
11 #include <linux/clk-provider.h>
57 clk_data->num = IMX7ULP_CLK_SCG1_END; in imx7ulp_clk_scg1_init()
58 hws = clk_data->hws; in imx7ulp_clk_scg1_init()
68 /* SCG1 */ in imx7ulp_clk_scg1_init()
111 …re", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk… in imx7ulp_clk_scg1_init()
113 …IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->… in imx7ulp_clk_scg1_init()
129 imx_check_clk_hws(hws, clk_data->num); in imx7ulp_clk_scg1_init()
133 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
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