Lines Matching +full:imx7ulp +full:- +full:scg1
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
8 #include <dt-bindings/clock/imx7ulp-clock.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include "imx7ulp-pinfunc.h"
15 interrupt-parent = <&intc>;
17 #address-cells = <1>;
18 #size-cells = <1>;
37 #address-cells = <1>;
38 #size-cells = <0>;
41 compatible = "arm,cortex-a7";
47 intc: interrupt-controller@40021000 {
48 compatible = "arm,cortex-a7-gic";
49 #interrupt-cells = <3>;
50 interrupt-controller;
55 rosc: clock-rosc {
56 compatible = "fixed-clock";
57 clock-frequency = <32768>;
58 clock-output-names = "rosc";
59 #clock-cells = <0>;
62 sosc: clock-sosc {
63 compatible = "fixed-clock";
64 clock-frequency = <24000000>;
65 clock-output-names = "sosc";
66 #clock-cells = <0>;
69 sirc: clock-sirc {
70 compatible = "fixed-clock";
71 clock-frequency = <16000000>;
72 clock-output-names = "sirc";
73 #clock-cells = <0>;
76 firc: clock-firc {
77 compatible = "fixed-clock";
78 clock-frequency = <48000000>;
79 clock-output-names = "firc";
80 #clock-cells = <0>;
83 upll: clock-upll {
84 compatible = "fixed-clock";
85 clock-frequency = <480000000>;
86 clock-output-names = "upll";
87 #clock-cells = <0>;
91 compatible = "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
97 edma1: dma-controller@40080000 {
98 #dma-cells = <2>;
99 compatible = "fsl,imx7ulp-edma";
102 dma-channels = <32>;
120 clock-names = "dma", "dmamux0";
126 compatible = "fsl,sec-v4.0";
127 #address-cells = <1>;
128 #size-cells = <1>;
132 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
133 clock-names = "aclk", "ipg";
136 compatible = "fsl,sec-v4.0-job-ring";
142 compatible = "fsl,sec-v4.0-job-ring";
149 compatible = "fsl,imx7ulp-lpuart";
153 clock-names = "ipg";
154 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART4>;
155 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
156 assigned-clock-rates = <24000000>;
161 compatible = "fsl,imx7ulp-lpuart";
165 clock-names = "ipg";
166 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>;
167 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
168 assigned-clock-rates = <48000000>;
173 compatible = "fsl,imx7ulp-pwm";
175 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM4>;
176 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
178 #pwm-cells = <3>;
183 compatible = "fsl,imx7ulp-tpm";
186 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
188 clock-names = "ipg", "per";
192 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
198 ahb-burst-config = <0x0>;
199 tx-burst-size-dword = <0x8>;
200 rx-burst-size-dword = <0x8>;
205 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc",
206 "fsl,imx6q-usbmisc";
207 #index-cells = <1>;
211 usbphy1: usb-phy@40350000 {
212 compatible = "fsl,imx7ulp-usbphy";
216 #phy-cells = <0>;
220 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
223 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
224 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
226 clock-names = "ipg", "ahb", "per";
227 bus-width = <4>;
228 fsl,tuning-start-tap = <20>;
229 fsl,tuning-step = <2>;
234 compatible = "fsl,imx7ulp-usdhc", "fsl,imx6sx-usdhc";
237 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
238 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
240 clock-names = "ipg", "ahb", "per";
241 bus-width = <4>;
242 fsl,tuning-start-tap = <20>;
243 fsl,tuning-step = <2>;
247 scg1: clock-controller@403e0000 { label
248 compatible = "fsl,imx7ulp-scg1";
252 clock-names = "rosc", "sosc", "sirc",
254 #clock-cells = <1>;
258 compatible = "fsl,imx7ulp-wdt";
262 assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG1>;
263 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
264 timeout-sec = <40>;
267 pcc2: clock-controller@403f0000 {
268 compatible = "fsl,imx7ulp-pcc2";
270 #clock-cells = <1>;
271 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
272 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
273 <&scg1 IMX7ULP_CLK_DDR_DIV>,
274 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
275 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
276 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
277 <&scg1 IMX7ULP_CLK_UPLL>,
278 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
279 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
280 <&scg1 IMX7ULP_CLK_ROSC>,
281 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
282 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
286 assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>;
287 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
290 smc1: clock-controller@40410000 {
291 compatible = "fsl,imx7ulp-smc1";
293 #clock-cells = <1>;
294 clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
295 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
296 clock-names = "divcore", "hsrun_divcore";
299 pcc3: clock-controller@40b30000 {
300 compatible = "fsl,imx7ulp-pcc3";
302 #clock-cells = <1>;
303 clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
304 <&scg1 IMX7ULP_CLK_NIC1_DIV>,
305 <&scg1 IMX7ULP_CLK_DDR_DIV>,
306 <&scg1 IMX7ULP_CLK_APLL_PFD2>,
307 <&scg1 IMX7ULP_CLK_APLL_PFD1>,
308 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
309 <&scg1 IMX7ULP_CLK_UPLL>,
310 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
311 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
312 <&scg1 IMX7ULP_CLK_ROSC>,
313 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
314 clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk",
322 compatible = "simple-bus";
323 #address-cells = <1>;
324 #size-cells = <1>;
329 compatible = "fsl,imx7ulp-lpi2c";
333 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
334 clock-names = "per", "ipg";
335 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C6>;
336 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
337 assigned-clock-rates = <48000000>;
342 compatible = "fsl,imx7ulp-lpi2c";
346 <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>;
347 clock-names = "per", "ipg";
348 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPI2C7>;
349 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
350 assigned-clock-rates = <48000000>;
355 compatible = "fsl,imx7ulp-lpuart";
359 clock-names = "ipg";
360 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>;
361 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
362 assigned-clock-rates = <48000000>;
367 compatible = "fsl,imx7ulp-lpuart";
371 clock-names = "ipg";
372 assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>;
373 assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>;
374 assigned-clock-rates = <48000000>;
378 memory-controller@40ab0000 {
379 compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc";
385 compatible = "fsl,imx7ulp-iomuxc1";
390 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
392 gpio-controller;
393 #gpio-cells = <2>;
395 interrupt-controller;
396 #interrupt-cells = <2>;
399 clock-names = "gpio", "port";
400 gpio-ranges = <&iomuxc1 0 0 20>;
404 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
406 gpio-controller;
407 #gpio-cells = <2>;
409 interrupt-controller;
410 #interrupt-cells = <2>;
413 clock-names = "gpio", "port";
414 gpio-ranges = <&iomuxc1 0 32 12>;
418 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
420 gpio-controller;
421 #gpio-cells = <2>;
423 interrupt-controller;
424 #interrupt-cells = <2>;
427 clock-names = "gpio", "port";
428 gpio-ranges = <&iomuxc1 0 64 16>;
432 compatible = "fsl,imx7ulp-gpio", "fsl,vf610-gpio";
434 gpio-controller;
435 #gpio-cells = <2>;
437 interrupt-controller;
438 #interrupt-cells = <2>;
441 clock-names = "gpio", "port";
442 gpio-ranges = <&iomuxc1 0 96 20>;
447 compatible = "simple-bus";
448 #address-cells = <1>;
449 #size-cells = <1>;
454 compatible = "fsl,imx7ulp-sim", "syscon";
459 compatible = "fsl,imx7ulp-ocotp", "syscon";
461 clocks = <&scg1 IMX7ULP_CLK_DUMMY>;
462 #address-cells = <1>;
463 #size-cells = <1>;