1*724ba675SRob Herring// SPDX-License-Identifier: GPL-2.0 2*724ba675SRob Herring// 3*724ba675SRob Herring// Copyright 2019 NXP 4*724ba675SRob Herring 5*724ba675SRob Herring/dts-v1/; 6*724ba675SRob Herring 7*724ba675SRob Herring#include "imx7ulp.dtsi" 8*724ba675SRob Herring#include <dt-bindings/input/input.h> 9*724ba675SRob Herring 10*724ba675SRob Herring/ { 11*724ba675SRob Herring model = "Embedded Artists i.MX7ULP COM"; 12*724ba675SRob Herring compatible = "ea,imx7ulp-com", "fsl,imx7ulp"; 13*724ba675SRob Herring 14*724ba675SRob Herring chosen { 15*724ba675SRob Herring stdout-path = &lpuart4; 16*724ba675SRob Herring }; 17*724ba675SRob Herring 18*724ba675SRob Herring memory@60000000 { 19*724ba675SRob Herring device_type = "memory"; 20*724ba675SRob Herring reg = <0x60000000 0x4000000>; 21*724ba675SRob Herring }; 22*724ba675SRob Herring}; 23*724ba675SRob Herring 24*724ba675SRob Herring&lpuart4 { 25*724ba675SRob Herring pinctrl-names = "default"; 26*724ba675SRob Herring pinctrl-0 = <&pinctrl_lpuart4>; 27*724ba675SRob Herring status = "okay"; 28*724ba675SRob Herring}; 29*724ba675SRob Herring 30*724ba675SRob Herring&usbotg1 { 31*724ba675SRob Herring pinctrl-names = "default"; 32*724ba675SRob Herring pinctrl-0 = <&pinctrl_usbotg1_id>; 33*724ba675SRob Herring srp-disable; 34*724ba675SRob Herring hnp-disable; 35*724ba675SRob Herring adp-disable; 36*724ba675SRob Herring status = "okay"; 37*724ba675SRob Herring}; 38*724ba675SRob Herring 39*724ba675SRob Herring&usdhc0 { 40*724ba675SRob Herring assigned-clocks = <&pcc2 IMX7ULP_CLK_USDHC0>; 41*724ba675SRob Herring assigned-clock-parents = <&scg1 IMX7ULP_CLK_APLL_PFD1>; 42*724ba675SRob Herring pinctrl-names = "default"; 43*724ba675SRob Herring pinctrl-0 = <&pinctrl_usdhc0>; 44*724ba675SRob Herring non-removable; 45*724ba675SRob Herring bus-width = <8>; 46*724ba675SRob Herring no-1-8-v; 47*724ba675SRob Herring status = "okay"; 48*724ba675SRob Herring}; 49*724ba675SRob Herring 50*724ba675SRob Herring&iomuxc1 { 51*724ba675SRob Herring pinctrl_lpuart4: lpuart4grp { 52*724ba675SRob Herring fsl,pins = < 53*724ba675SRob Herring IMX7ULP_PAD_PTC3__LPUART4_RX 0x3 54*724ba675SRob Herring IMX7ULP_PAD_PTC2__LPUART4_TX 0x3 55*724ba675SRob Herring >; 56*724ba675SRob Herring }; 57*724ba675SRob Herring 58*724ba675SRob Herring pinctrl_usbotg1_id: otg1idgrp { 59*724ba675SRob Herring fsl,pins = < 60*724ba675SRob Herring IMX7ULP_PAD_PTC13__USB0_ID 0x10003 61*724ba675SRob Herring >; 62*724ba675SRob Herring }; 63*724ba675SRob Herring 64*724ba675SRob Herring pinctrl_usdhc0: usdhc0grp { 65*724ba675SRob Herring fsl,pins = < 66*724ba675SRob Herring IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 67*724ba675SRob Herring IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042 68*724ba675SRob Herring IMX7ULP_PAD_PTD3__SDHC0_D7 0x43 69*724ba675SRob Herring IMX7ULP_PAD_PTD4__SDHC0_D6 0x43 70*724ba675SRob Herring IMX7ULP_PAD_PTD5__SDHC0_D5 0x43 71*724ba675SRob Herring IMX7ULP_PAD_PTD6__SDHC0_D4 0x43 72*724ba675SRob Herring IMX7ULP_PAD_PTD7__SDHC0_D3 0x43 73*724ba675SRob Herring IMX7ULP_PAD_PTD8__SDHC0_D2 0x43 74*724ba675SRob Herring IMX7ULP_PAD_PTD9__SDHC0_D1 0x43 75*724ba675SRob Herring IMX7ULP_PAD_PTD10__SDHC0_D0 0x43 76*724ba675SRob Herring IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42 77*724ba675SRob Herring >; 78*724ba675SRob Herring }; 79*724ba675SRob Herring}; 80