1f6525302SAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2f6525302SAnson Huang%YAML 1.2 3f6525302SAnson Huang--- 4f6525302SAnson Huang$id: http://devicetree.org/schemas/clock/imx7ulp-pcc-clock.yaml# 5f6525302SAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6f6525302SAnson Huang 7*33cd7c6fSKrzysztof Kozlowskititle: Freescale i.MX7ULP Peripheral Clock Control (PCC) modules Clock Controller 8f6525302SAnson Huang 9f6525302SAnson Huangmaintainers: 10f6525302SAnson Huang - A.s. Dong <aisheng.dong@nxp.com> 11f6525302SAnson Huang 12f6525302SAnson Huangdescription: | 13f6525302SAnson Huang i.MX7ULP Clock functions are under joint control of the System 14f6525302SAnson Huang Clock Generation (SCG) modules, Peripheral Clock Control (PCC) 15f6525302SAnson Huang modules, and Core Mode Controller (CMC)1 blocks 16f6525302SAnson Huang 17f6525302SAnson Huang The clocking scheme provides clear separation between M4 domain 18f6525302SAnson Huang and A7 domain. Except for a few clock sources shared between two 19f6525302SAnson Huang domains, such as the System Oscillator clock, the Slow IRC (SIRC), 20f6525302SAnson Huang and and the Fast IRC clock (FIRCLK), clock sources and clock 21f6525302SAnson Huang management are separated and contained within each domain. 22f6525302SAnson Huang 23f6525302SAnson Huang M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules. 24f6525302SAnson Huang A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules. 25f6525302SAnson Huang 26f6525302SAnson Huang Note: this binding doc is only for A7 clock domain. 27f6525302SAnson Huang 28f6525302SAnson Huang The Peripheral Clock Control (PCC) is responsible for clock selection, 29f6525302SAnson Huang optional division and clock gating mode for peripherals in their 30f6525302SAnson Huang respected power domain. 31f6525302SAnson Huang 32f6525302SAnson Huang The clock consumer should specify the desired clock by having the clock 33f6525302SAnson Huang ID in its "clocks" phandle cell. 34f6525302SAnson Huang See include/dt-bindings/clock/imx7ulp-clock.h for the full list of 35f6525302SAnson Huang i.MX7ULP clock IDs of each module. 36f6525302SAnson Huang 37f6525302SAnson Huangproperties: 38f6525302SAnson Huang compatible: 39f6525302SAnson Huang enum: 40f6525302SAnson Huang - fsl,imx7ulp-pcc2 41f6525302SAnson Huang - fsl,imx7ulp-pcc3 42f6525302SAnson Huang 43f6525302SAnson Huang reg: 44f6525302SAnson Huang maxItems: 1 45f6525302SAnson Huang 46f6525302SAnson Huang '#clock-cells': 47f6525302SAnson Huang const: 1 48f6525302SAnson Huang 49f6525302SAnson Huang clocks: 50f6525302SAnson Huang items: 51f6525302SAnson Huang - description: nic1 bus clock 52f6525302SAnson Huang - description: nic1 clock 53f6525302SAnson Huang - description: ddr clock 54f6525302SAnson Huang - description: apll pfd2 55f6525302SAnson Huang - description: apll pfd1 56f6525302SAnson Huang - description: apll pfd0 57f6525302SAnson Huang - description: usb pll 58f6525302SAnson Huang - description: system osc bus clock 59f6525302SAnson Huang - description: fast internal reference clock bus 60f6525302SAnson Huang - description: rtc osc 61f6525302SAnson Huang - description: system pll bus clock 62f6525302SAnson Huang 63f6525302SAnson Huang clock-names: 64f6525302SAnson Huang items: 65f6525302SAnson Huang - const: nic1_bus_clk 66f6525302SAnson Huang - const: nic1_clk 67f6525302SAnson Huang - const: ddr_clk 68f6525302SAnson Huang - const: apll_pfd2 69f6525302SAnson Huang - const: apll_pfd1 70f6525302SAnson Huang - const: apll_pfd0 71f6525302SAnson Huang - const: upll 72f6525302SAnson Huang - const: sosc_bus_clk 73f6525302SAnson Huang - const: firc_bus_clk 74f6525302SAnson Huang - const: rosc 75f6525302SAnson Huang - const: spll_bus_clk 76f6525302SAnson Huang 77f6525302SAnson Huangrequired: 78f6525302SAnson Huang - compatible 79f6525302SAnson Huang - reg 80f6525302SAnson Huang - '#clock-cells' 81f6525302SAnson Huang - clocks 82f6525302SAnson Huang - clock-names 83f6525302SAnson Huang 84f6525302SAnson HuangadditionalProperties: false 85f6525302SAnson Huang 86f6525302SAnson Huangexamples: 87f6525302SAnson Huang - | 88f6525302SAnson Huang #include <dt-bindings/clock/imx7ulp-clock.h> 89f6525302SAnson Huang #include <dt-bindings/interrupt-controller/arm-gic.h> 90f6525302SAnson Huang 91f6525302SAnson Huang clock-controller@403f0000 { 92f6525302SAnson Huang compatible = "fsl,imx7ulp-pcc2"; 93f6525302SAnson Huang reg = <0x403f0000 0x10000>; 94f6525302SAnson Huang #clock-cells = <1>; 95f6525302SAnson Huang clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>, 96f6525302SAnson Huang <&scg1 IMX7ULP_CLK_NIC1_DIV>, 97f6525302SAnson Huang <&scg1 IMX7ULP_CLK_DDR_DIV>, 98f6525302SAnson Huang <&scg1 IMX7ULP_CLK_APLL_PFD2>, 99f6525302SAnson Huang <&scg1 IMX7ULP_CLK_APLL_PFD1>, 100f6525302SAnson Huang <&scg1 IMX7ULP_CLK_APLL_PFD0>, 101f6525302SAnson Huang <&scg1 IMX7ULP_CLK_UPLL>, 102f6525302SAnson Huang <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, 103f6525302SAnson Huang <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, 104f6525302SAnson Huang <&scg1 IMX7ULP_CLK_ROSC>, 105f6525302SAnson Huang <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; 106f6525302SAnson Huang clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", 107f6525302SAnson Huang "apll_pfd2", "apll_pfd1", "apll_pfd0", 108f6525302SAnson Huang "upll", "sosc_bus_clk", "firc_bus_clk", 109f6525302SAnson Huang "rosc", "spll_bus_clk"; 110f6525302SAnson Huang }; 111