xref: /linux/Documentation/devicetree/bindings/clock/imx7ulp-scg-clock.yaml (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1f6525302SAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2f6525302SAnson Huang%YAML 1.2
3f6525302SAnson Huang---
4f6525302SAnson Huang$id: http://devicetree.org/schemas/clock/imx7ulp-scg-clock.yaml#
5f6525302SAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml#
6f6525302SAnson Huang
7*33cd7c6fSKrzysztof Kozlowskititle: Freescale i.MX7ULP System Clock Generation (SCG) modules Clock Controller
8f6525302SAnson Huang
9f6525302SAnson Huangmaintainers:
10f6525302SAnson Huang  - A.s. Dong <aisheng.dong@nxp.com>
11f6525302SAnson Huang
12f6525302SAnson Huangdescription: |
13f6525302SAnson Huang  i.MX7ULP Clock functions are under joint control of the System
14f6525302SAnson Huang  Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
15f6525302SAnson Huang  modules, and Core Mode Controller (CMC)1 blocks
16f6525302SAnson Huang
17f6525302SAnson Huang  The clocking scheme provides clear separation between M4 domain
18f6525302SAnson Huang  and A7 domain. Except for a few clock sources shared between two
19f6525302SAnson Huang  domains, such as the System Oscillator clock, the Slow IRC (SIRC),
20f6525302SAnson Huang  and and the Fast IRC clock (FIRCLK), clock sources and clock
21f6525302SAnson Huang  management are separated and contained within each domain.
22f6525302SAnson Huang
23f6525302SAnson Huang  M4 clock management consists of SCG0, PCC0, PCC1, and CMC0 modules.
24f6525302SAnson Huang  A7 clock management consists of SCG1, PCC2, PCC3, and CMC1 modules.
25f6525302SAnson Huang
26f6525302SAnson Huang  Note: this binding doc is only for A7 clock domain.
27f6525302SAnson Huang
28f6525302SAnson Huang  The System Clock Generation (SCG) is responsible for clock generation
29f6525302SAnson Huang  and distribution across this device. Functions performed by the SCG
30f6525302SAnson Huang  include: clock reference selection, generation of clock used to derive
31f6525302SAnson Huang  processor, system, peripheral bus and external memory interface clocks,
32f6525302SAnson Huang  source selection for peripheral clocks and control of power saving
33f6525302SAnson Huang  clock gating mode.
34f6525302SAnson Huang
35f6525302SAnson Huang  The clock consumer should specify the desired clock by having the clock
36f6525302SAnson Huang  ID in its "clocks" phandle cell.
37f6525302SAnson Huang  See include/dt-bindings/clock/imx7ulp-clock.h for the full list of
38f6525302SAnson Huang  i.MX7ULP clock IDs of each module.
39f6525302SAnson Huang
40f6525302SAnson Huangproperties:
41f6525302SAnson Huang  compatible:
42f6525302SAnson Huang    const: fsl,imx7ulp-scg1
43f6525302SAnson Huang
44f6525302SAnson Huang  reg:
45f6525302SAnson Huang    maxItems: 1
46f6525302SAnson Huang
47f6525302SAnson Huang  '#clock-cells':
48f6525302SAnson Huang    const: 1
49f6525302SAnson Huang
50f6525302SAnson Huang  clocks:
51f6525302SAnson Huang    items:
52f6525302SAnson Huang      - description: rtc osc
53f6525302SAnson Huang      - description: system osc
54f6525302SAnson Huang      - description: slow internal reference clock
55f6525302SAnson Huang      - description: fast internal reference clock
56f6525302SAnson Huang      - description: usb PLL
57f6525302SAnson Huang
58f6525302SAnson Huang  clock-names:
59f6525302SAnson Huang    items:
60f6525302SAnson Huang      - const: rosc
61f6525302SAnson Huang      - const: sosc
62f6525302SAnson Huang      - const: sirc
63f6525302SAnson Huang      - const: firc
64f6525302SAnson Huang      - const: upll
65f6525302SAnson Huang
66f6525302SAnson Huangrequired:
67f6525302SAnson Huang  - compatible
68f6525302SAnson Huang  - reg
69f6525302SAnson Huang  - '#clock-cells'
70f6525302SAnson Huang  - clocks
71f6525302SAnson Huang  - clock-names
72f6525302SAnson Huang
73f6525302SAnson HuangadditionalProperties: false
74f6525302SAnson Huang
75f6525302SAnson Huangexamples:
76f6525302SAnson Huang  - |
77f6525302SAnson Huang    #include <dt-bindings/clock/imx7ulp-clock.h>
78f6525302SAnson Huang    #include <dt-bindings/interrupt-controller/arm-gic.h>
79f6525302SAnson Huang
80f6525302SAnson Huang    clock-controller@403e0000 {
81f6525302SAnson Huang        compatible = "fsl,imx7ulp-scg1";
82f6525302SAnson Huang        reg = <0x403e0000 0x10000>;
83f6525302SAnson Huang        clocks = <&rosc>, <&sosc>, <&sirc>,
84f6525302SAnson Huang                 <&firc>, <&upll>;
85f6525302SAnson Huang        clock-names = "rosc", "sosc", "sirc",
86f6525302SAnson Huang                      "firc", "upll";
87f6525302SAnson Huang        #clock-cells = <1>;
88f6525302SAnson Huang    };
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