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/linux/drivers/i2c/busses/
H A Di2c-mt65xx.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/dma-mapping.h>
14 #include <linux/i2c.h>
28 #define I2C_RS_TRANSFER (1 << 4)
29 #define I2C_ARB_LOST (1 << 3)
30 #define I2C_HS_NACKERR (1 << 2)
31 #define I2C_ACKERR (1 << 1)
32 #define I2C_TRANSAC_COMP (1 << 0)
33 #define I2C_TRANSAC_START (1 << 0)
34 #define I2C_RS_MUL_CNFG (1 << 15)
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H A Di2c-pxa.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * I2C adapter for the PXA I2C bus access.
8 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
13 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
14 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
24 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-pxa.h>
38 /* I2C register field definitions */
39 #define IBMR_SDAS (1 << 0)
40 #define IBMR_SCLS (1 << 1)
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H A Di2c-xiic.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * i2c-xiic.c
4 * Copyright (c) 2002-2007 Xilinx Inc.
5 * Copyright (c) 2009-2010 Intel Corporation
24 #include <linux/i2c.h>
27 #include <linux/platform_data/i2c-xiic.h>
34 #define DRIVER_NAME "xiic-i2c"
51 REG_VALUES_400KHZ = 1,
56 * struct xiic_i2c - Internal representation of the XIIC I2C bus
67 * @endianness: big/little-endian byte order
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H A Di2c-octeon-core.c2 * (C) Copyright 2009-2010
5 * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7 * This file contains the shared part of the driver for the i2c adapter in
16 #include <linux/i2c.h>
22 #include "i2c-octeon-core.h"
31 struct octeon_i2c *i2c = dev_id; in octeon_i2c_isr() local
33 i2c->int_disable(i2c); in octeon_i2c_isr()
34 wake_up(&i2c->queue); in octeon_i2c_isr()
39 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c) in octeon_i2c_test_iflg() argument
41 return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG); in octeon_i2c_test_iflg()
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H A Di2c-jz4780.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Ingenic JZ4780 I2C bus driver
5 * Copyright (C) 2006 - 2009 Ingenic Semiconductor Inc.
15 #include <linux/i2c.h>
68 #define JZ4780_I2C_CTRL_SPDS BIT(1)
76 #define JZ4780_I2C_STA_TFNF BIT(1)
91 #define JZ4780_I2C_INTST_RXOF BIT(1)
104 #define JZ4780_I2C_INTM_MRXOF BIT(1)
113 #define JZ4780_I2CSHCNT_ADJUST(n) (((n) - 8) < 6 ? 6 : ((n) - 8))
114 #define JZ4780_I2CSLCNT_ADJUST(n) (((n) - 1) < 8 ? 8 : ((n) - 1))
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H A Di2c-s3c2410.c1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/i2c/busses/i2c-s3c2410.c
7 * S3C2410 I2C Controller
13 #include <linux/i2c.h>
34 #include <linux/platform_data/i2c-s3c2410.h>
36 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
44 #define S3C2410_IICCON_ACKEN (1 << 7)
46 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
47 #define S3C2410_IICCON_IRQEN (1 << 5)
48 #define S3C2410_IICCON_IRQPEND (1 << 4)
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H A Di2c-digicolor.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * I2C bus driver for Conexant Digicolor SoCs
13 #include <linux/i2c.h>
29 #define II_CMD_START 1
38 #define II_CMD_STATUS_ACK_GOOD 1
71 static void dc_i2c_cmd(struct dc_i2c *i2c, u8 cmd) in dc_i2c_cmd() argument
73 writeb_relaxed(cmd | II_COMMAND_GO, i2c->regs + II_COMMAND); in dc_i2c_cmd()
78 u8 addr = (msg->addr & 0x7f) << 1; in dc_i2c_addr_cmd()
80 if (msg->flags & I2C_M_RD) in dc_i2c_addr_cmd()
81 addr |= 1; in dc_i2c_addr_cmd()
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H A Di2c-viai2c-common.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 #include "i2c-viai2c-common.h"
5 int viai2c_wait_bus_not_busy(struct viai2c *i2c) in viai2c_wait_bus_not_busy() argument
10 while (!(readw(i2c->base + VIAI2C_REG_CSR) & VIAI2C_CSR_READY_MASK)) { in viai2c_wait_bus_not_busy()
12 dev_warn(i2c->dev, "timeout waiting for bus ready\n"); in viai2c_wait_bus_not_busy()
13 return -EBUSY; in viai2c_wait_bus_not_busy()
22 static int viai2c_write(struct viai2c *i2c, struct i2c_msg *pmsg, int last) in viai2c_write() argument
24 u16 val, tcr_val = i2c->tcr; in viai2c_write()
26 i2c->last = last; in viai2c_write()
28 if (pmsg->len == 0) { in viai2c_write()
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H A Di2c-mchp-pci1xxxx.c1 // SPDX-License-Identifier: GPL-2.0
3 * Microchip PCI1XXXX I2C adapter driver for PCIe Switch
4 * which has I2C controller in one of its downstream functions
6 * Copyright (C) 2021 - 2022 Microchip Technology Inc.
14 #include <linux/i2c.h>
15 #include <linux/i2c-smbus.h>
42 #define SMB_CORE_CMD_M_PROCEED BIT(1)
97 #define SMB_CONFIG1_RESET BIT(1)
103 * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock
104 * periods that make up the low phase of the I2C/SMBus bus clock at X KHz.
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H A Di2c-cgbc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Congatec Board Controller I2C busses driver
9 #include <linux/i2c.h>
33 * Reference code defines 1kHz as min freq and 6.1MHz as max freq.
34 * But in practice, the board controller limits the frequency to 1MHz, and the
35 * 1kHz is not functional (minimal working freq is 50kHz).
39 #define CGBC_I2C_FREQ_MAX_HZ 1000000 /* 1 MHz */
118 struct i2c_algo_cgbc_data *algo_data = adap->algo_data; in cgbc_i2c_get_status()
119 struct cgbc_i2c_data *i2c = i2c_get_adapdata(adap); in cgbc_i2c_get_status() local
120 struct cgbc_device_data *cgbc = i2c->cgbc; in cgbc_i2c_get_status()
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H A Di2c-synquacer.c1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/i2c.h>
25 /* I2C register address definitions */
35 /* I2C register bit definitions */
37 #define SYNQUACER_I2C_BSR_GCA BIT(1) // General Call Address
46 #define SYNQUACER_I2C_BCR_INTE BIT(1) // Interrupt Enable
61 #define SYNQUACER_I2C_BC2R_SDAL BIT(1) // SDA Low Drive
66 #define SYNQUACER_I2C_BUS_CLK_FR(rate) (((rate) / 20000000) + 1)
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
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H A Di2c-mpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * This is a combined i2c adapter and algorithm driver for the
5 * the same I2C unit (8240, 8245, 85xx).
7 * Copyright (C) 2003-2004 Humboldt Solutions Ltd, adrian@humboldt.co.uk
25 #include <linux/i2c.h>
59 MPC_I2C_ACTION_START = 1,
109 void (*setup)(struct device_node *node, struct mpc_i2c *i2c, u32 clock);
112 static inline void writeccr(struct mpc_i2c *i2c, u32 x) in writeccr() argument
114 writeb(x, i2c->base + MPC_I2C_CR); in writeccr()
122 static void mpc_i2c_fixup(struct mpc_i2c *i2c) in mpc_i2c_fixup() argument
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/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-facebook-cmm.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,cmm-bmc", "aspeed,ast2500";
22 * PCA9548 (1-0077) provides 8 channels for connecting to
35 * PCA9548 (2-0071) provides 8 channels for connecting to
48 * PCA9548 (8-0077) provides 8 channels and the first 4
61 * 2 PCA9548 (18-0070 & 18-0073), 16 channels connecting
62 * to Line Card #1.
82 * 2 PCA9548 (19-0070 & 19-0073), 16 channels connecting
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H A Daspeed-bmc-facebook-minipack.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2500-facebook-netbmc-common.dtsi"
9 compatible = "facebook,minipack-bmc", "aspeed,ast2500";
23 * i2c switch 2-0070, pca9548, 8 child channels assigned
24 * with bus number 16-23.
36 * i2c switch 8-0070, pca9548, 8 child channels assigned
37 * with bus number 24-31.
49 * i2c switch 9-0070, pca9548, 8 child channels assigned
50 * with bus number 32-39.
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H A Daspeed-bmc-facebook-fuji.dts1 // SPDX-License-Identifier: GPL-2.0+
4 /dts-v1/;
6 #include <dt-bindings/leds/common.h>
7 #include "ast2600-facebook-netbmc-common.dtsi"
11 compatible = "facebook,fuji-bmc", "aspeed,ast2600";
15 * PCA9548 (2-0070) provides 8 channels connecting to
28 * PCA9548 (8-0070) provides 8 channels connecting to
41 * PCA9548 (11-0077) provides 8 channels connecting to
54 * PCA9548 (24-0071) provides 8 channels connecting to
55 * PDB-Left.
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H A Dibm-power9-dual.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 #address-cells = <1>;
8 #size-cells = <1>;
9 chip-id = <0>;
16 i2c@1800 {
17 compatible = "ibm,fsi-i2c-master";
19 #address-cells = <1>;
20 #size-cells = <0>;
22 cfam0_i2c0: i2c-bus@0 {
26 cfam0_i2c1: i2c-bus@1 {
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/linux/Documentation/i2c/
H A Di2c-sysfs.rst1 .. SPDX-License-Identifier: GPL-2.0
4 Linux I2C Sysfs
10 I2C topology can be complex because of the existence of I2C MUX
11 (I2C Multiplexer). The Linux
12 kernel abstracts the MUX channels into logical I2C bus numbers. However, there
13 is a gap of knowledge to map from the I2C bus physical number and MUX topology
14 to logical I2C bus number. This doc is aimed to fill in this gap, so the
16 the concept of logical I2C buses in the kernel, by knowing the physical I2C
17 topology and navigating through the I2C sysfs in Linux shell. This knowledge is
18 useful and essential to use ``i2c-tools`` for the purpose of development and
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/linux/Documentation/devicetree/bindings/i2c/
H A Dst,stm32-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I2C controller embedded in STMicroelectronics STM32 I2C platform
10 - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
13 - $ref: /schemas/i2c/i2c-controller.yaml#
14 - if:
19 - st,stm32f7-i2c
20 - st,stm32mp13-i2c
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H A Dnvidia,tegra20-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Thierry Reding <thierry.reding@gmail.com>
9 - Jon Hunter <jonathanh@nvidia.com>
11 title: NVIDIA Tegra I2C controller driver
16 - description: Tegra20 has 4 generic I2C controller. This can support
17 master and slave mode of I2C communication. The i2c-tegra driver
18 only support master mode of I2C communication. Driver of I2C
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H A Drenesas,rcar-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car I2C Controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
15 - items:
16 - enum:
17 - renesas,i2c-r8a7778 # R-Car M1A
18 - renesas,i2c-r8a7779 # R-Car H1
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/linux/sound/soc/codecs/
H A Dwm2000.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm2000.c -- WM2000 ALSA Soc Audio driver
5 * Copyright 2008-2011 Wolfson Microelectronics PLC.
13 * system-specific calibration information. If supplied as a
14 * sequence of ASCII-encoded hexidecimal bytes this can be converted
17 * perl -e 'while (<>) { s/[\r\n]+// ; printf("%c", hex($_)); }'
29 #include <linux/i2c.h>
55 ANC_BYPASS = 1,
61 struct i2c_client *i2c; member
69 unsigned int anc_active:1;
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/linux/drivers/media/pci/ddbridge/
H A Dddbridge-i2c.c1 // SPDX-License-Identifier: GPL-2.0
3 * ddbridge-i2c.c: Digital Devices bridge i2c driver
5 * Copyright (C) 2010-2017 Digital Devices GmbH
20 #include <linux/i2c.h>
25 #include "ddbridge-i2c.h"
26 #include "ddbridge-regs.h"
27 #include "ddbridge-io.h"
31 static int ddb_i2c_cmd(struct ddb_i2c *i2c, u32 adr, u32 cmd) in ddb_i2c_cmd() argument
33 struct ddb *dev = i2c->dev; in ddb_i2c_cmd()
37 ddbwritel(dev, (adr << 9) | cmd, i2c->regs + I2C_COMMAND); in ddb_i2c_cmd()
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/linux/arch/mips/boot/dts/mscc/
H A Djaguar2_pcb110.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
11 model = "Jaguar2 Cu8-Sfp16 PCB110 Reference Board";
12 compatible = "mscc,jr2-pcb110", "mscc,jr2";
45 i2c0_imux: i2c0-imux {
46 compatible = "i2c-mux-pinctrl";
47 #address-cells = <1>;
48 #size-cells = <0>;
49 i2c-parent = <&i2c0>;
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/linux/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_i2c.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Internal I2C bus driver for NetUP Universal Dual DVB-CI
52 } __packed __aligned(1);
63 } __packed __aligned(1);
65 irqreturn_t netup_i2c_interrupt(struct netup_i2c *i2c) in netup_i2c_interrupt() argument
71 spin_lock_irqsave(&i2c->lock, flags); in netup_i2c_interrupt()
72 reg = readw(&i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
73 writew(reg & ~TWI_IRQEN, &i2c->regs->twi_ctrl0_stat); in netup_i2c_interrupt()
74 dev_dbg(i2c->adap.dev.parent, in netup_i2c_interrupt()
77 dev_dbg(i2c->adap.dev.parent, in netup_i2c_interrupt()
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/linux/Documentation/devicetree/bindings/net/
H A Dmctp-i2c-controller.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/mctp-i2c-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MCTP I2C transport
10 - Matt Johnston <matt@codeconstruct.com.au>
13 An mctp-i2c-controller defines a local MCTP endpoint on an I2C controller.
14 MCTP I2C is specified by DMTF DSP0237.
16 An mctp-i2c-controller must be attached to an I2C adapter which supports
17 slave functionality. I2C busses (either directly or as subordinate mux
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