2  * (C) Copyright 2009-2010
5  * Portions Copyright (C) 2010 - 2016 Cavium, Inc.
7  * This file contains the shared part of the driver for the i2c adapter in
16 #include <linux/i2c.h>
22 #include "i2c-octeon-core.h"
31 	struct octeon_i2c *i2c = dev_id;  in octeon_i2c_isr()  local
33 	i2c->int_disable(i2c);  in octeon_i2c_isr()
34 	wake_up(&i2c->queue);  in octeon_i2c_isr()
39 static bool octeon_i2c_test_iflg(struct octeon_i2c *i2c)  in octeon_i2c_test_iflg()  argument
41 	return (octeon_i2c_ctl_read(i2c) & TWSI_CTL_IFLG);  in octeon_i2c_test_iflg()
45  * octeon_i2c_wait - wait for the IFLG to be set
46  * @i2c: The struct octeon_i2c
50 static int octeon_i2c_wait(struct octeon_i2c *i2c)  in octeon_i2c_wait()  argument
58 	if (i2c->broken_irq_mode) {  in octeon_i2c_wait()
59 		u64 end = get_jiffies_64() + i2c->adap.timeout;  in octeon_i2c_wait()
61 		while (!octeon_i2c_test_iflg(i2c) &&  in octeon_i2c_wait()
65 		return octeon_i2c_test_iflg(i2c) ? 0 : -ETIMEDOUT;  in octeon_i2c_wait()
68 	i2c->int_enable(i2c);  in octeon_i2c_wait()
69 	time_left = wait_event_timeout(i2c->queue, octeon_i2c_test_iflg(i2c),  in octeon_i2c_wait()
70 				       i2c->adap.timeout);  in octeon_i2c_wait()
71 	i2c->int_disable(i2c);  in octeon_i2c_wait()
73 	if (i2c->broken_irq_check && !time_left &&  in octeon_i2c_wait()
74 	    octeon_i2c_test_iflg(i2c)) {  in octeon_i2c_wait()
75 		dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");  in octeon_i2c_wait()
76 		i2c->broken_irq_mode = true;  in octeon_i2c_wait()
81 		return -ETIMEDOUT;  in octeon_i2c_wait()
86 static bool octeon_i2c_hlc_test_valid(struct octeon_i2c *i2c)  in octeon_i2c_hlc_test_valid()  argument
88 	return (__raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c)) & SW_TWSI_V) == 0;  in octeon_i2c_hlc_test_valid()
91 static void octeon_i2c_hlc_int_clear(struct octeon_i2c *i2c)  in octeon_i2c_hlc_int_clear()  argument
94 	octeon_i2c_write_int(i2c, TWSI_INT_ST_INT | TWSI_INT_TS_INT);  in octeon_i2c_hlc_int_clear()
98  * Cleanup low-level state & enable high-level controller.
100 static void octeon_i2c_hlc_enable(struct octeon_i2c *i2c)  in octeon_i2c_hlc_enable()  argument
105 	if (i2c->hlc_enabled)  in octeon_i2c_hlc_enable()
107 	i2c->hlc_enabled = true;  in octeon_i2c_hlc_enable()
109 	while (1) {  in octeon_i2c_hlc_enable()
110 		val = octeon_i2c_ctl_read(i2c);  in octeon_i2c_hlc_enable()
116 			octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_hlc_enable()
126 	octeon_i2c_ctl_write(i2c, TWSI_CTL_CE | TWSI_CTL_AAK | TWSI_CTL_ENAB);  in octeon_i2c_hlc_enable()
129 static void octeon_i2c_hlc_disable(struct octeon_i2c *i2c)  in octeon_i2c_hlc_disable()  argument
131 	if (!i2c->hlc_enabled)  in octeon_i2c_hlc_disable()
134 	i2c->hlc_enabled = false;  in octeon_i2c_hlc_disable()
135 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_hlc_disable()
139  * octeon_i2c_hlc_wait - wait for an HLC operation to complete
140  * @i2c: The struct octeon_i2c
142  * Returns 0 on success, otherwise -ETIMEDOUT.
144 static int octeon_i2c_hlc_wait(struct octeon_i2c *i2c)  in octeon_i2c_hlc_wait()  argument
152 	if (i2c->broken_irq_mode) {  in octeon_i2c_hlc_wait()
153 		u64 end = get_jiffies_64() + i2c->adap.timeout;  in octeon_i2c_hlc_wait()
155 		while (!octeon_i2c_hlc_test_valid(i2c) &&  in octeon_i2c_hlc_wait()
159 		return octeon_i2c_hlc_test_valid(i2c) ? 0 : -ETIMEDOUT;  in octeon_i2c_hlc_wait()
162 	i2c->hlc_int_enable(i2c);  in octeon_i2c_hlc_wait()
163 	time_left = wait_event_timeout(i2c->queue,  in octeon_i2c_hlc_wait()
164 				       octeon_i2c_hlc_test_valid(i2c),  in octeon_i2c_hlc_wait()
165 				       i2c->adap.timeout);  in octeon_i2c_hlc_wait()
166 	i2c->hlc_int_disable(i2c);  in octeon_i2c_hlc_wait()
168 		octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_wait()
170 	if (i2c->broken_irq_check && !time_left &&  in octeon_i2c_hlc_wait()
171 	    octeon_i2c_hlc_test_valid(i2c)) {  in octeon_i2c_hlc_wait()
172 		dev_err(i2c->dev, "broken irq connection detected, switching to polling mode.\n");  in octeon_i2c_hlc_wait()
173 		i2c->broken_irq_mode = true;  in octeon_i2c_hlc_wait()
178 		return -ETIMEDOUT;  in octeon_i2c_hlc_wait()
182 static int octeon_i2c_check_status(struct octeon_i2c *i2c, int final_read)  in octeon_i2c_check_status()  argument
191 	if (i2c->hlc_enabled)  in octeon_i2c_check_status()
192 		stat = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_check_status()
194 		stat = octeon_i2c_stat_read(i2c);  in octeon_i2c_check_status()
205 	/* ACK allowed on pre-terminal bytes only */  in octeon_i2c_check_status()
209 		return -EIO;  in octeon_i2c_check_status()
215 		return -EIO;  in octeon_i2c_check_status()
222 		return -EAGAIN;  in octeon_i2c_check_status()
229 		return -EOPNOTSUPP;  in octeon_i2c_check_status()
239 		return -EOPNOTSUPP;  in octeon_i2c_check_status()
243 		return -EIO;  in octeon_i2c_check_status()
247 		return -ENXIO;  in octeon_i2c_check_status()
250 		mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));  in octeon_i2c_check_status()
253 		octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));  in octeon_i2c_check_status()
254 		return -EIO;  in octeon_i2c_check_status()
256 		dev_err(i2c->dev, "unhandled state: %d\n", stat);  in octeon_i2c_check_status()
257 		return -EIO;  in octeon_i2c_check_status()
261 static int octeon_i2c_recovery(struct octeon_i2c *i2c)  in octeon_i2c_recovery()  argument
265 	ret = i2c_recover_bus(&i2c->adap);  in octeon_i2c_recovery()
267 		/* recover failed, try hardware re-init */  in octeon_i2c_recovery()
268 		ret = octeon_i2c_init_lowlevel(i2c);  in octeon_i2c_recovery()
273  * octeon_i2c_start - send START to the bus
274  * @i2c: The struct octeon_i2c
278 static int octeon_i2c_start(struct octeon_i2c *i2c)  in octeon_i2c_start()  argument
283 	octeon_i2c_hlc_disable(i2c);  in octeon_i2c_start()
285 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STA);  in octeon_i2c_start()
286 	ret = octeon_i2c_wait(i2c);  in octeon_i2c_start()
290 	stat = octeon_i2c_stat_read(i2c);  in octeon_i2c_start()
297 	ret = octeon_i2c_recovery(i2c);  in octeon_i2c_start()
298 	return (ret) ? ret : -EAGAIN;  in octeon_i2c_start()
302 static void octeon_i2c_stop(struct octeon_i2c *i2c)  in octeon_i2c_stop()  argument
304 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_STP);  in octeon_i2c_stop()
308  * octeon_i2c_read - receive data from the bus via low-level controller
309  * @i2c: The struct octeon_i2c
319 static int octeon_i2c_read(struct octeon_i2c *i2c, int target,  in octeon_i2c_read()  argument
325 	octeon_i2c_data_write(i2c, (target << 1) | 1);  in octeon_i2c_read()
326 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_read()
328 	result = octeon_i2c_wait(i2c);  in octeon_i2c_read()
333 	result = octeon_i2c_check_status(i2c, false);  in octeon_i2c_read()
346 		if ((i + 1 == length) && !(recv_len && i == 0))  in octeon_i2c_read()
351 			octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_read()
353 			octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB | TWSI_CTL_AAK);  in octeon_i2c_read()
355 		result = octeon_i2c_wait(i2c);  in octeon_i2c_read()
359 		data[i] = octeon_i2c_data_read(i2c, &result);  in octeon_i2c_read()
364 				return -EPROTO;  in octeon_i2c_read()
368 		result = octeon_i2c_check_status(i2c, final_read);  in octeon_i2c_read()
377  * octeon_i2c_write - send data to the bus via low-level controller
378  * @i2c: The struct octeon_i2c
387 static int octeon_i2c_write(struct octeon_i2c *i2c, int target,  in octeon_i2c_write()  argument
392 	octeon_i2c_data_write(i2c, target << 1);  in octeon_i2c_write()
393 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_write()
395 	result = octeon_i2c_wait(i2c);  in octeon_i2c_write()
400 		result = octeon_i2c_check_status(i2c, false);  in octeon_i2c_write()
404 		octeon_i2c_data_write(i2c, data[i]);  in octeon_i2c_write()
405 		octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_write()
407 		result = octeon_i2c_wait(i2c);  in octeon_i2c_write()
415 /* high-level-controller pure read of up to 8 bytes */
416 static int octeon_i2c_hlc_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_read()  argument
421 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_read()
422 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_read()
426 	cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_read()
435 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_read()
436 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_read()
440 	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_read()
442 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_read()
444 	for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)  in octeon_i2c_hlc_read()
448 		cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_read()
449 		for (i = 0; i  < msgs[0].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_read()
457 /* high-level-controller pure write of up to 8 bytes */
458 static int octeon_i2c_hlc_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_write()  argument
463 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_write()
464 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_write()
468 	cmd |= (u64)(msgs[0].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_write()
477 	for (i = 0, j = msgs[0].len - 1; i  < msgs[0].len && i < 4; i++, j--)  in octeon_i2c_hlc_write()
483 		for (i = 0; i < msgs[0].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_write()
485 		octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_write()
488 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_write()
489 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_write()
493 	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_write()
495 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_write()
501 /* high-level-controller composite write+read, msg0=addr, msg1=data */
502 static int octeon_i2c_hlc_comp_read(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_comp_read()  argument
507 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_comp_read()
511 	cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_comp_read()
525 		cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_read()
526 		octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_comp_read()
531 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_comp_read()
532 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_comp_read()
534 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_comp_read()
538 	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_comp_read()
540 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_comp_read()
542 	for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)  in octeon_i2c_hlc_comp_read()
543 		msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;  in octeon_i2c_hlc_comp_read()
545 	if (msgs[1].len > 4) {  in octeon_i2c_hlc_comp_read()
546 		cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_comp_read()
547 		for (i = 0; i  < msgs[1].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_comp_read()
548 			msgs[1].buf[j] = (cmd >> (8 * i)) & 0xff;  in octeon_i2c_hlc_comp_read()
555 /* high-level-controller composite write+write, m[0]len<=2, m[1]len<=8 */
556 static int octeon_i2c_hlc_comp_write(struct octeon_i2c *i2c, struct i2c_msg *msgs)  in octeon_i2c_hlc_comp_write()  argument
562 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_hlc_comp_write()
566 	cmd |= (u64)(msgs[1].len - 1) << SW_TWSI_SIZE_SHIFT;  in octeon_i2c_hlc_comp_write()
579 		cmd |= (u64)msgs[0].buf[1] << SW_TWSI_IA_SHIFT;  in octeon_i2c_hlc_comp_write()
584 	for (i = 0, j = msgs[1].len - 1; i  < msgs[1].len && i < 4; i++, j--)  in octeon_i2c_hlc_comp_write()
585 		cmd |= (u64)msgs[1].buf[j] << (8 * i);  in octeon_i2c_hlc_comp_write()
587 	if (msgs[1].len > 4) {  in octeon_i2c_hlc_comp_write()
588 		for (i = 0; i < msgs[1].len - 4 && i < 4; i++, j--)  in octeon_i2c_hlc_comp_write()
589 			ext |= (u64)msgs[1].buf[j] << (8 * i);  in octeon_i2c_hlc_comp_write()
593 		octeon_i2c_writeq_flush(ext, i2c->twsi_base + OCTEON_REG_SW_TWSI_EXT(i2c));  in octeon_i2c_hlc_comp_write()
595 	octeon_i2c_hlc_int_clear(i2c);  in octeon_i2c_hlc_comp_write()
596 	octeon_i2c_writeq_flush(cmd, i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_comp_write()
598 	ret = octeon_i2c_hlc_wait(i2c);  in octeon_i2c_hlc_comp_write()
602 	cmd = __raw_readq(i2c->twsi_base + OCTEON_REG_SW_TWSI(i2c));  in octeon_i2c_hlc_comp_write()
604 		return octeon_i2c_check_status(i2c, false);  in octeon_i2c_hlc_comp_write()
611  * octeon_i2c_xfer - The driver's xfer function
620 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_xfer()  local
623 	if (IS_LS_FREQ(i2c->twsi_freq)) {  in octeon_i2c_xfer()
624 		if (num == 1) {  in octeon_i2c_xfer()
627 					ret = octeon_i2c_hlc_read(i2c, msgs);  in octeon_i2c_xfer()
629 					ret = octeon_i2c_hlc_write(i2c, msgs);  in octeon_i2c_xfer()
634 			    (msgs[1].flags & I2C_M_RECV_LEN) == 0 &&  in octeon_i2c_xfer()
636 			    msgs[1].len > 0 && msgs[1].len <= 8 &&  in octeon_i2c_xfer()
637 			    msgs[0].addr == msgs[1].addr) {  in octeon_i2c_xfer()
638 				if (msgs[1].flags & I2C_M_RD)  in octeon_i2c_xfer()
639 					ret = octeon_i2c_hlc_comp_read(i2c, msgs);  in octeon_i2c_xfer()
641 					ret = octeon_i2c_hlc_comp_write(i2c, msgs);  in octeon_i2c_xfer()
650 		/* zero-length messages are not supported */  in octeon_i2c_xfer()
651 		if (!pmsg->len) {  in octeon_i2c_xfer()
652 			ret = -EOPNOTSUPP;  in octeon_i2c_xfer()
656 		ret = octeon_i2c_start(i2c);  in octeon_i2c_xfer()
660 		if (pmsg->flags & I2C_M_RD)  in octeon_i2c_xfer()
661 			ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,  in octeon_i2c_xfer()
662 					      &pmsg->len, pmsg->flags & I2C_M_RECV_LEN);  in octeon_i2c_xfer()
664 			ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,  in octeon_i2c_xfer()
665 					       pmsg->len);  in octeon_i2c_xfer()
667 	octeon_i2c_stop(i2c);  in octeon_i2c_xfer()
673 void octeon_i2c_set_clock(struct octeon_i2c *i2c)  in octeon_i2c_set_clock()  argument
685 	is_plat_otx2 = octeon_i2c_is_otx2(to_pci_dev(i2c->dev));  in octeon_i2c_set_clock()
690 		if (!IS_LS_FREQ(i2c->twsi_freq))  in octeon_i2c_set_clock()
702 		for (mdiv_idx = 15; mdiv_idx >= mdiv_min && delta_hz != 0; mdiv_idx--) {  in octeon_i2c_set_clock()
707 			tclk = i2c->twsi_freq * (mdiv_idx + 1) * ds;  in octeon_i2c_set_clock()
708 			tclk *= (1 << ndiv_idx);  in octeon_i2c_set_clock()
710 				thp_base = (i2c->sys_freq / tclk) - 2;  in octeon_i2c_set_clock()
712 				thp_base = (i2c->sys_freq / (tclk * 2)) - 1;  in octeon_i2c_set_clock()
714 			for (inc = 0; inc <= 1; inc++) {  in octeon_i2c_set_clock()
720 					foscl = i2c->sys_freq / (thp_idx + 2);  in octeon_i2c_set_clock()
722 					foscl = i2c->sys_freq /  in octeon_i2c_set_clock()
723 						(2 * (thp_idx + 1));  in octeon_i2c_set_clock()
724 				foscl = foscl / (1 << ndiv_idx);  in octeon_i2c_set_clock()
725 				foscl = foscl / (mdiv_idx + 1) / ds;  in octeon_i2c_set_clock()
726 				if (foscl > i2c->twsi_freq)  in octeon_i2c_set_clock()
728 				diff = abs(foscl - i2c->twsi_freq);  in octeon_i2c_set_clock()
743 	octeon_i2c_reg_write(i2c, SW_TWSI_OP_TWSI_CLK, thp);  in octeon_i2c_set_clock()
744 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);  in octeon_i2c_set_clock()
748 		mode = __raw_readq(i2c->twsi_base + OCTEON_REG_MODE(i2c));  in octeon_i2c_set_clock()
750 		if (!IS_LS_FREQ(i2c->twsi_freq))  in octeon_i2c_set_clock()
754 		octeon_i2c_writeq_flush(mode, i2c->twsi_base + OCTEON_REG_MODE(i2c));  in octeon_i2c_set_clock()
758 int octeon_i2c_init_lowlevel(struct octeon_i2c *i2c)  in octeon_i2c_init_lowlevel()  argument
764 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);  in octeon_i2c_init_lowlevel()
766 	for (tries = 10; tries && status != STAT_IDLE; tries--) {  in octeon_i2c_init_lowlevel()
767 		udelay(1);  in octeon_i2c_init_lowlevel()
768 		status = octeon_i2c_stat_read(i2c);  in octeon_i2c_init_lowlevel()
774 		dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n",  in octeon_i2c_init_lowlevel()
776 		return -EIO;  in octeon_i2c_init_lowlevel()
780 	octeon_i2c_hlc_enable(i2c);  in octeon_i2c_init_lowlevel()
781 	octeon_i2c_hlc_disable(i2c);  in octeon_i2c_init_lowlevel()
787 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_get_scl()  local
790 	state = octeon_i2c_read_int(i2c);  in octeon_i2c_get_scl()
796 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_set_scl()  local
798 	octeon_i2c_write_int(i2c, val ? 0 : TWSI_INT_SCL_OVR);  in octeon_i2c_set_scl()
803 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_get_sda()  local
806 	state = octeon_i2c_read_int(i2c);  in octeon_i2c_get_sda()
812 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_prepare_recovery()  local
814 	octeon_i2c_hlc_disable(i2c);  in octeon_i2c_prepare_recovery()
815 	octeon_i2c_reg_write(i2c, SW_TWSI_EOP_TWSI_RST, 0);  in octeon_i2c_prepare_recovery()
823 	octeon_i2c_ctl_write(i2c, TWSI_CTL_ENAB);  in octeon_i2c_prepare_recovery()
825 	octeon_i2c_write_int(i2c, 0);  in octeon_i2c_prepare_recovery()
830 	struct octeon_i2c *i2c = i2c_get_adapdata(adap);  in octeon_i2c_unprepare_recovery()  local
837 	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR | TWSI_INT_SCL_OVR);  in octeon_i2c_unprepare_recovery()
839 	octeon_i2c_write_int(i2c, TWSI_INT_SDA_OVR);  in octeon_i2c_unprepare_recovery()
841 	octeon_i2c_write_int(i2c, 0);  in octeon_i2c_unprepare_recovery()