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/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
9 * e1000e_get_bus_info_pcie - Get PCIe bus information
10 * @hw: pointer to the HW structure
16 s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) in e1000e_get_bus_info_pcie() argument
18 struct pci_dev *pdev = hw->adapter->pdev; in e1000e_get_bus_info_pcie()
19 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie()
20 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
24 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
27 bus->width = (enum e1000_bus_width)FIELD_GET(PCI_EXP_LNKSTA_NLW, in e1000e_get_bus_info_pcie()
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H A D82571.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
22 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
23 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
24 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
25 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
26 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
28 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
29 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
30 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
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H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
8 static s32 e1000_access_phy_wakeup_reg_bm(struct e1000_hw *hw, u32 offset,
11 static s32 e1000_access_phy_debug_regs_hv(struct e1000_hw *hw, u32 offset,
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
38 * @hw: pointer to the HW structure
44 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw) in e1000e_check_reset_block_generic() argument
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
55 * @hw: pointer to the HW structure
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H A Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
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/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
11 static s32 e1000_check_downshift(struct e1000_hw *hw);
12 static s32 e1000_check_polarity(struct e1000_hw *hw,
14 static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
15 static void e1000_clear_vfta(struct e1000_hw *hw);
16 static s32 e1000_config_dsp_after_link_change(struct e1000_hw *hw,
18 static s32 e1000_config_fc_after_link_up(struct e1000_hw *hw);
19 static s32 e1000_detect_gig_phy(struct e1000_hw *hw);
20 static s32 e1000_get_auto_rd_done(struct e1000_hw *hw);
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/linux/Documentation/devicetree/bindings/serial/
H A Dst,stm32-uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/st,stm32-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 - Erwan Le Ray <erwan.leray@foss.st.com>
15 - st,stm32-uart
16 - st,stm32f7-uart
17 - st,stm32h7-uart
34 st,hw-flow-ctrl:
35 description: enable hardware flow control (deprecated)
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H A Dst,asc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Patrice Chotard <patrice.chotard@foss.st.com>
13 - $ref: serial.yaml#
28 st,hw-flow-ctrl:
29 description: When set, enable hardware flow control.
32 st,force-m1:
33 description: When set, force asc to be in Mode-1. This is recommended for
38 - compatible
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/linux/drivers/net/ethernet/intel/igb/
H A De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
15 static s32 igb_set_default_fc(struct e1000_hw *hw);
16 static void igb_set_fc_watermarks(struct e1000_hw *hw);
19 * igb_get_bus_info_pcie - Get PCIe bus information
20 * @hw: pointer to the HW structure
26 s32 igb_get_bus_info_pcie(struct e1000_hw *hw) in igb_get_bus_info_pcie() argument
28 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
33 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
35 ret_val = igb_read_pcie_cap_reg(hw, in igb_get_bus_info_pcie()
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H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
10 static s32 igb_phy_setup_autoneg(struct e1000_hw *hw);
11 static void igb_phy_force_speed_duplex_setup(struct e1000_hw *hw,
13 static s32 igb_wait_autoneg(struct e1000_hw *hw);
14 static s32 igb_set_master_slave_mode(struct e1000_hw *hw);
31 * igb_check_reset_block - Check if PHY reset is blocked
32 * @hw: pointer to the HW structure
38 s32 igb_check_reset_block(struct e1000_hw *hw) in igb_check_reset_block() argument
48 * igb_get_phy_id - Retrieve the PHY ID and revision
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H A De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
46 static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw);
47 static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw);
48 static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw);
49 static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw);
50 static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw);
51 static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw);
55 /* Due to a hw errata, if the host tries to configure the VFTA register
61 * igb_write_vfta_i350 - Write value to VLAN filter table
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/linux/drivers/net/ethernet/intel/igc/
H A Digc_phy.c1 // SPDX-License-Identifier: GPL-2.0
8 * igc_check_reset_block - Check if PHY reset is blocked
9 * @hw: pointer to the HW structure
15 s32 igc_check_reset_block(struct igc_hw *hw) in igc_check_reset_block() argument
26 * igc_get_phy_id - Retrieve the PHY ID and revision
27 * @hw: pointer to the HW structure
32 s32 igc_get_phy_id(struct igc_hw *hw) in igc_get_phy_id() argument
34 struct igc_phy_info *phy = &hw->phy; in igc_get_phy_id()
38 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id); in igc_get_phy_id()
42 phy->id = (u32)(phy_id << 16); in igc_get_phy_id()
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H A Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
14 * @hw: pointer to the HW structure
19 static s32 igc_reset_hw_base(struct igc_hw *hw) in igc_reset_hw_base() argument
22 u32 ctrl; in igc_reset_hw_base() local
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
27 ret_val = igc_disable_pcie_master(hw); in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); in igc_reset_hw_base()
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/linux/arch/arm/boot/dts/st/
H A Dstm32mp157a-iot-box.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include "stm32mp157a-stinger96.dtsi"
11 compatible = "shiratech,stm32mp157a-iot-box", "st,stm32mp157";
13 wlan_pwr: regulator-wlan {
14 compatible = "regulator-fixed";
16 regulator-name = "wl-reg";
17 regulator-min-microvolt = <3300000>;
18 regulator-max-microvolt = <3300000>;
21 enable-active-high;
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en_accel/
H A Dipsec_offload.c1 // SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
44 (mdev->priv.steering->mode == MLX5_FLOW_STEERING_MODE_DMFS || in mlx5_ipsec_device_caps()
45 (mdev->priv.steering->mode == MLX5_FLOW_STEERING_MODE_SMFS && in mlx5_ipsec_device_caps()
85 * because we use up to 24 bit in flow table metadata in mlx5_ipsec_device_caps()
96 struct mlx5_accel_esp_xfrm_attrs *attrs = &sa_entry->attrs; in mlx5e_ipsec_packet_setup()
100 if (attrs->replay_esn.trigger) { in mlx5e_ipsec_packet_setup()
103 if (attrs->dir == XFRM_DEV_OFFLOAD_IN) { in mlx5e_ipsec_packet_setup()
105 attrs->replay_esn.replay_window); in mlx5e_ipsec_packet_setup()
110 attrs->replay_esn.esn); in mlx5e_ipsec_packet_setup()
118 * in flow steering to perform matching against. Please be in mlx5e_ipsec_packet_setup()
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/linux/drivers/net/ethernet/netronome/nfp/flower/
H A Dcmsg.c1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */
18 return (struct nfp_flower_cmsg_hdr *)skb->data; in nfp_flower_cmsg_get_hdr()
35 ch->pad = 0; in nfp_flower_cmsg_alloc()
36 ch->version = NFP_FLOWER_CMSG_VER1; in nfp_flower_cmsg_alloc()
37 ch->type = type; in nfp_flower_cmsg_alloc()
55 memset(msg->reserved, 0, sizeof(msg->reserved)); in nfp_flower_cmsg_mac_repr_start()
56 msg->num_ports = num_ports; in nfp_flower_cmsg_mac_repr_start()
69 msg->ports[idx].idx = idx; in nfp_flower_cmsg_mac_repr_add()
70 msg->ports[idx].info = nbi & NFP_FLOWER_CMSG_MAC_REPR_NBI; in nfp_flower_cmsg_mac_repr_add()
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/linux/drivers/net/ethernet/marvell/
H A Dsky2.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * of the original driver such as link fail-over and link management because
19 #include <linux/dma-mapping.h>
54 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
70 #define RING_NEXT(x, s) (((x)+1) & ((s)-1))
77 static int debug = -1; /* defaults above */
85 static int disable_msi = -1;
94 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
95 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
96 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
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H A Dsky2.h1 /* SPDX-License-Identifier: GPL-2.0 */
30 /* Yukon-2 */
32 PCI_Y2_PIG_ENA = 1<<31, /* Enable Plug-in-Go (YUKON-2) */
33 PCI_Y2_DLL_DIS = 1<<30, /* Disable PCI DLL (YUKON-2) */
34 PCI_SW_PWR_ON_RST= 1<<30, /* SW Power on Reset (Yukon-EX) */
35 PCI_Y2_PHY2_COMA = 1<<29, /* Set PHY 2 to Coma Mode (YUKON-2) */
36 PCI_Y2_PHY1_COMA = 1<<28, /* Set PHY 1 to Coma Mode (YUKON-2) */
37 PCI_Y2_PHY2_POWD = 1<<27, /* Set PHY 2 to Power Down (YUKON-2) */
38 PCI_Y2_PHY1_POWD = 1<<26, /* Set PHY 1 to Power Down (YUKON-2) */
60 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
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H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
167 IS_HW_ERR = 1<<31, /* Interrupt HW Error */
215 /* B2_IRQM_HWE_MSK 32 bit IRQ Moderation HW Error Mask */
262 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
264 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
265 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
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/linux/drivers/usb/serial/
H A Dark3116.c1 // SPDX-License-Identifier: GPL-2.0+
9 * - implements a driver for the arkmicro ark3116 chipset (vendor=0x6547,
10 * productid=0x0232) (used in a datacable called KQ-U8A)
12 * Supports full modem status lines, break, hardware flow control. Does not
13 * support software flow control, since I do not know how to enable it in hw.
52 struct usb_device *dev = serial->dev; in is_irda()
53 if (le16_to_cpu(dev->descriptor.idVendor) == 0x18ec && in is_irda()
54 le16_to_cpu(dev->descriptor.idProduct) == 0x3118) in is_irda()
62 /* protects hw register updates */
82 result = usb_control_msg(serial->dev, in ark3116_write_reg()
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/linux/samples/pktgen/
H A Dpktgen_sample03_burst_single_flow.sh2 # SPDX-License-Identifier: GPL-2.0
4 # Script for max single flow performance
5 # - If correctly tuned[1], single CPU 10G wirespeed small pkts is possible[2]
7 # Using pktgen "burst" option (use -b $N)
8 # - To boost max performance
9 # - Avail since: kernel v3.18
10 # * commit 38b2cf2982dc73 ("net: pktgen: packet bursting via skb->xmit_more")
11 # - This avoids writing the HW tailptr on every driver xmit
12 # - The performance boost is impressive, see commit and blog [2]
14 # Notice: On purpose generates a single (UDP) flow towards target,
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/linux/drivers/net/ethernet/atheros/atlx/
H A Datl2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2006 - 2007 Atheros Corporation. All rights reserved.
4 * Copyright(c) 2007 - 2008 Chris Snook <csnook@redhat.com>
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
12 #include <linux/dma-mapping.h>
47 * atl2_pci_tbl - PCI Device ID Table
59 * atl2_sw_init - Initialize general software structures (struct atl2_adapter)
68 struct atl2_hw *hw = &adapter->hw; in atl2_sw_init() local
69 struct pci_dev *pdev = adapter->pdev; in atl2_sw_init()
72 hw->vendor_id = pdev->vendor; in atl2_sw_init()
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H A Datl1.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
4 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
5 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
8 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
21 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
37 #include <linux/dma-mapping.h>
84 #define OPTION_UNSET -1
93 * Valid Range: 10-65535
131 *value = opt->def; in atl1_validate_option()
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/linux/drivers/pwm/
H A Dpwm-dwc-core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2020 Intel Corporation
22 #include "pwm-dwc.h"
43 u32 ctrl; in __dwc_pwm_configure_timer() local
49 * periods and check are the result within HW limits between 1 and in __dwc_pwm_configure_timer()
52 tmp = DIV_ROUND_CLOSEST_ULL(state->duty_cycle, dwc->clk_ns); in __dwc_pwm_configure_timer()
54 return -ERANGE; in __dwc_pwm_configure_timer()
55 low = tmp - 1; in __dwc_pwm_configure_timer()
57 tmp = DIV_ROUND_CLOSEST_ULL(state->period - state->duty_cycle, in __dwc_pwm_configure_timer()
58 dwc->clk_ns); in __dwc_pwm_configure_timer()
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/linux/drivers/net/ethernet/sun/
H A Dcassini.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* cassini register map: 2M memory mapped in 32-bit memory space accessible as
30 * 32-bit words. there is no i/o port access. REG_ addresses are
62 /* top level interrupts [0-9] are auto-cleared to 0 when the status
63 * register is read. second level interrupts [13 - 18] are cleared at
64 * the source. tx completion register 3 is replicated in [19 - 31]
97 hw use */
100 of descr spaces for hw
104 len of non-reassembly pkt
183 #define BIM_CFG_64BIT_DISABLE 0x004 /* disable 64-bit mode */
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_virtchnl_fdir.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (C) 2021-2023, Intel Corporation. */
95 * Return: 0 on success, and -EINVAL on error.
100 struct ice_pf *pf = vf->pf; in ice_vc_fdir_param_check()
102 if (!test_bit(ICE_FLAG_FD_ENA, pf->flags)) in ice_vc_fdir_param_check()
103 return -EINVAL; in ice_vc_fdir_param_check()
105 if (!test_bit(ICE_VF_STATE_ACTIVE, vf->vf_states)) in ice_vc_fdir_param_check()
106 return -EINVAL; in ice_vc_fdir_param_check()
108 if (!(vf->driver_caps & VIRTCHNL_VF_OFFLOAD_FDIR_PF)) in ice_vc_fdir_param_check()
109 return -EINVAL; in ice_vc_fdir_param_check()
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