1*28e4c31eSRaphael Gallais-Pou# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*28e4c31eSRaphael Gallais-Pou%YAML 1.2 3*28e4c31eSRaphael Gallais-Pou--- 4*28e4c31eSRaphael Gallais-Pou$id: http://devicetree.org/schemas/serial/st,asc.yaml# 5*28e4c31eSRaphael Gallais-Pou$schema: http://devicetree.org/meta-schemas/core.yaml# 6*28e4c31eSRaphael Gallais-Pou 7*28e4c31eSRaphael Gallais-Poutitle: STMicroelectronics STi SoCs Serial Port 8*28e4c31eSRaphael Gallais-Pou 9*28e4c31eSRaphael Gallais-Poumaintainers: 10*28e4c31eSRaphael Gallais-Pou - Patrice Chotard <patrice.chotard@foss.st.com> 11*28e4c31eSRaphael Gallais-Pou 12*28e4c31eSRaphael Gallais-PouallOf: 13*28e4c31eSRaphael Gallais-Pou - $ref: serial.yaml# 14*28e4c31eSRaphael Gallais-Pou 15*28e4c31eSRaphael Gallais-Pouproperties: 16*28e4c31eSRaphael Gallais-Pou compatible: 17*28e4c31eSRaphael Gallais-Pou const: st,asc 18*28e4c31eSRaphael Gallais-Pou 19*28e4c31eSRaphael Gallais-Pou reg: 20*28e4c31eSRaphael Gallais-Pou maxItems: 1 21*28e4c31eSRaphael Gallais-Pou 22*28e4c31eSRaphael Gallais-Pou interrupts: 23*28e4c31eSRaphael Gallais-Pou maxItems: 1 24*28e4c31eSRaphael Gallais-Pou 25*28e4c31eSRaphael Gallais-Pou clocks: 26*28e4c31eSRaphael Gallais-Pou maxItems: 1 27*28e4c31eSRaphael Gallais-Pou 28*28e4c31eSRaphael Gallais-Pou st,hw-flow-ctrl: 29*28e4c31eSRaphael Gallais-Pou description: When set, enable hardware flow control. 30*28e4c31eSRaphael Gallais-Pou type: boolean 31*28e4c31eSRaphael Gallais-Pou 32*28e4c31eSRaphael Gallais-Pou st,force-m1: 33*28e4c31eSRaphael Gallais-Pou description: When set, force asc to be in Mode-1. This is recommended for 34*28e4c31eSRaphael Gallais-Pou high bit rates above 19.2K. 35*28e4c31eSRaphael Gallais-Pou type: boolean 36*28e4c31eSRaphael Gallais-Pou 37*28e4c31eSRaphael Gallais-Pourequired: 38*28e4c31eSRaphael Gallais-Pou - compatible 39*28e4c31eSRaphael Gallais-Pou - reg 40*28e4c31eSRaphael Gallais-Pou - interrupts 41*28e4c31eSRaphael Gallais-Pou - clocks 42*28e4c31eSRaphael Gallais-Pou 43*28e4c31eSRaphael Gallais-PouunevaluatedProperties: false 44*28e4c31eSRaphael Gallais-Pou 45*28e4c31eSRaphael Gallais-Pouexamples: 46*28e4c31eSRaphael Gallais-Pou - | 47*28e4c31eSRaphael Gallais-Pou #include <dt-bindings/clock/stih407-clks.h> 48*28e4c31eSRaphael Gallais-Pou #include <dt-bindings/interrupt-controller/arm-gic.h> 49*28e4c31eSRaphael Gallais-Pou serial@9830000 { 50*28e4c31eSRaphael Gallais-Pou compatible = "st,asc"; 51*28e4c31eSRaphael Gallais-Pou reg = <0x9830000 0x2c>; 52*28e4c31eSRaphael Gallais-Pou interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 53*28e4c31eSRaphael Gallais-Pou clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; 54*28e4c31eSRaphael Gallais-Pou }; 55*28e4c31eSRaphael Gallais-Pou... 56