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/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-hs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm's USB HS PHY
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 if:
17 - qcom,usb-hs-phy-apq8064
18 - qcom,usb-hs-phy-msm8660
19 - qcom,usb-hs-phy-msm8960
[all …]
H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
21 'tx-p2p-microvolt-names' property must be provided and contain
24 tx-p2p-microvolt-names:
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H A Dphy-stm32-usbphyc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller
22 |_ PHY port#2 ----| |________________
27 - Amelie Delaunay <amelie.delaunay@foss.st.com>
31 const: st,stm32mp1-usbphyc
42 "#address-cells":
45 "#size-cells":
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H A Dbrcm,sr-usb-combo-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/brcm,sr-usb-combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom Stingray USB PHY
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
16 - brcm,sr-usb-combo-phy
17 - brcm,sr-usb-hs-phy
22 '#phy-cells':
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H A Dnvidia,tegra20-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra20-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra USB PHY
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
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H A Dfsl,imx8mq-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/fsl,imx8mq-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Jun <jun.li@nxp.com>
15 - enum:
16 - fsl,imx8mq-usb-phy
17 - fsl,imx8mp-usb-phy
18 - items:
19 - const: fsl,imx95-usb-phy
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H A Drenesas,rcar-gen2-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/renesas,rcar-gen2-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car Gen2 USB PHY
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
15 - enum:
16 - renesas,usb-phy-r8a7742 # RZ/G1H
17 - renesas,usb-phy-r8a7743 # RZ/G1M
18 - renesas,usb-phy-r8a7744 # RZ/G1N
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/linux/drivers/phy/qualcomm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
8 default y if USB_EHCI_HCD_PLATFORM || USB_OHCI_HCD_PLATFORM
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
57 if PHY_QCOM_QMP
66 select DRM_AUX_BRIDGE if DRM_BRIDGE
98 tristate "Qualcomm QMP USB PHY Driver"
102 Enable this to support the QMP USB PHY transceiver that is used
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H A Dphy-qcom-snps-femto-v2.c1 // SPDX-License-Identifier: GPL-2.0
82 "vdda-pll", "vdda33", "vdda18",
110 * struct qcom_snps_hsphy - snps hs phy attributes
115 * @base: iomapped memory space for snps hs phy
121 * @phy_initialized: if PHY has been initialized correctly
143 struct device *dev = hsphy->dev; in qcom_snps_hsphy_clk_init()
145 hsphy->num_clks = 2; in qcom_snps_hsphy_clk_init()
146 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); in qcom_snps_hsphy_clk_init()
147 if (!hsphy->clks) in qcom_snps_hsphy_clk_init()
148 return -ENOMEM; in qcom_snps_hsphy_clk_init()
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/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,rcar-usb2-clock-sel.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car USB 2.0 clock selector
10 - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
13 If you connect an external clock to the USB_EXTAL pin only, you should set
15 If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
19 Case 1: An external clock connects to R-Car SoC
20 +----------+ +--- R-Car ---------------------+
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/linux/Documentation/devicetree/bindings/usb/
H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtu3.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
26 $ref: usb.yaml#
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H A Dchipidea,usb2-imx.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/chipidea,usb2-imx.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP USB2 ChipIdea USB controller
10 - Xu Yang <xu.yang_2@nxp.com>
15 - enum:
16 - fsl,imx27-usb
17 - items:
18 - enum:
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H A Dqcom,dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
12 # Use the combined qcom,snps-dwc3 instead
21 - compatible
26 - enum:
27 - qcom,ipq4019-dwc3
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H A Dqcom,snps-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Describes the Qualcomm USB block, based on Synopsys DWC3.
19 const: qcom,snps-dwc3
21 - compatible
26 - enum:
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/linux/drivers/usb/cdns3/
H A Dcdns3-gadget.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2019 Cadence.
6 * Copyright (C) 2017-2018 NXP
14 #include <linux/usb/gadget.h>
15 #include <linux/dma-direction.h>
18 * USBSS-DEV register interface.
23 * struct cdns3_usb_regs - device controller registers.
29 * @usb_ien: USB Interrupt Enable.
30 * @usb_ists: USB Interrupt Status.
53 * @buf_addr: Address for On-chip Buffer operations.
[all …]
H A DKconfig2 tristate "Cadence USB Support"
3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA
4 select USB_XHCI_PLATFORM if USB_XHCI_HCD
7 Say Y here if your system has a Cadence USBSS or USBSSP
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
14 if USB_CDNS_SUPPORT
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
[all …]
/linux/drivers/usb/gadget/
H A Dconfig.c1 // SPDX-License-Identifier: GPL-2.0+
3 * usb/gadget/config.c -- simplify building config descriptors
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/usb/composite.h>
19 #include <linux/usb/otg.h>
22 * usb_descriptor_fillbuf - fill buffer with descriptors
28 * negative error code if they can't all be copied. Useful when
39 if (!src) in usb_descriptor_fillbuf()
40 return -EINVAL; in usb_descriptor_fillbuf()
[all …]
/linux/drivers/usb/gadget/legacy/
H A Daudio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * audio.c -- Audio gadget driver
13 #include <linux/usb/composite.h>
15 #define DRIVER_DESC "Linux USB Audio Gadget"
23 /* Playback(USB-IN) Default Stereo - Fl/Fr */
39 /* Playback bInterval for HS/SS (1-4: fixed, 0: auto) */
43 "Playback bInterval for HS/SS (1-4: fixed, 0: auto)");
45 /* Capture(USB-OUT) Default Stereo - Fl/Fr */
61 /* capture bInterval for HS/SS (1-4: fixed, 0: auto) */
65 "Capture bInterval for HS/SS (1-4: fixed, 0: auto)");
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/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt1 OMAP HS USB Host
5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
[all …]
/linux/drivers/usb/dwc2/
H A Dgadget.c1 // SPDX-License-Identifier: GPL-2.0
11 * S3C USB2.0 High-speed / OtG driver
19 #include <linux/dma-mapping.h>
26 #include <linux/usb/ch9.h>
27 #include <linux/usb/gadget.h>
28 #include <linux/usb/phy.h>
29 #include <linux/usb/composite.h>
64 if (dir_in) in index_to_ep()
65 return hsotg->eps_in[ep_index]; in index_to_ep()
67 return hsotg->eps_out[ep_index]; in index_to_ep()
[all …]
H A Dpci.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * pci.c - DesignWare HS OTG Controller PCI driver
5 * Copyright (C) 2004-2013 Synopsys, Inc.
20 #include <linux/usb.h>
22 #include <linux/usb/hcd.h>
23 #include <linux/usb/ch11.h>
25 #include <linux/usb/usb_phy_generic.h>
29 static const char dwc2_driver_name[] = "dwc2-pci";
37 * dwc2_pci_remove() - Provides the cleanup entry points for the DWC_otg PCI
46 platform_device_unregister(glue->dwc2); in dwc2_pci_remove()
[all …]
/linux/drivers/usb/dwc3/
H A Ddwc3-qcom-legacy.c1 // SPDX-License-Identifier: GPL-2.0
4 * Inspired by dwc3-of-simple.c
20 #include <linux/usb/of.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/usb.h>
27 /* USB QSCRATCH Hardware registers */
121 if (enable) { in dwc3_qcom_vbus_override_enable()
122 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
124 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
127 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL, in dwc3_qcom_vbus_override_enable()
[all …]
/linux/drivers/usb/gadget/udc/
H A Damd5536udc_pci.c1 // SPDX-License-Identifier: GPL-2.0+
3 * amd5536udc_pci.c -- AMD 5536 UDC high/full speed USB device controller
5 * Copyright (C) 2005-2007 AMD (https://www.amd.com)
11 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
18 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
26 * Synopsys device controller IP (different than HS OTG IP) in UDCs
32 #define UDC_MOD_DESCRIPTION "AMD 5536 UDC - USB Device Controller"
52 static const char name[] = "amd5536udc-pci";
61 usb_del_gadget_udc(&udc->gadget); in udc_pci_remove()
63 if (WARN_ON(dev->driver)) in udc_pci_remove()
[all …]
/linux/drivers/usb/host/
H A Docteon-hcd.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
41 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
110 * The application must program this register as part of the O2P USB core
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
[all …]

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