1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12description: 13 Describes the Qualcomm USB block, based on Synopsys DWC3. 14 15select: 16 properties: 17 compatible: 18 contains: 19 const: qcom,snps-dwc3 20 required: 21 - compatible 22 23properties: 24 compatible: 25 items: 26 - enum: 27 - qcom,ipq4019-dwc3 28 - qcom,ipq5018-dwc3 29 - qcom,ipq5332-dwc3 30 - qcom,ipq5424-dwc3 31 - qcom,ipq6018-dwc3 32 - qcom,ipq8064-dwc3 33 - qcom,ipq8074-dwc3 34 - qcom,ipq9574-dwc3 35 - qcom,msm8953-dwc3 36 - qcom,msm8994-dwc3 37 - qcom,msm8996-dwc3 38 - qcom,msm8998-dwc3 39 - qcom,qcm2290-dwc3 40 - qcom,qcs404-dwc3 41 - qcom,qcs615-dwc3 42 - qcom,qcs8300-dwc3 43 - qcom,qdu1000-dwc3 44 - qcom,sa8775p-dwc3 45 - qcom,sar2130p-dwc3 46 - qcom,sc7180-dwc3 47 - qcom,sc7280-dwc3 48 - qcom,sc8180x-dwc3 49 - qcom,sc8180x-dwc3-mp 50 - qcom,sc8280xp-dwc3 51 - qcom,sc8280xp-dwc3-mp 52 - qcom,sdm660-dwc3 53 - qcom,sdm670-dwc3 54 - qcom,sdm845-dwc3 55 - qcom,sdx55-dwc3 56 - qcom,sdx65-dwc3 57 - qcom,sdx75-dwc3 58 - qcom,sm4250-dwc3 59 - qcom,sm6115-dwc3 60 - qcom,sm6125-dwc3 61 - qcom,sm6350-dwc3 62 - qcom,sm6375-dwc3 63 - qcom,sm8150-dwc3 64 - qcom,sm8250-dwc3 65 - qcom,sm8350-dwc3 66 - qcom,sm8450-dwc3 67 - qcom,sm8550-dwc3 68 - qcom,sm8650-dwc3 69 - qcom,x1e80100-dwc3 70 - const: qcom,snps-dwc3 71 72 reg: 73 maxItems: 1 74 75 power-domains: 76 maxItems: 1 77 78 required-opps: 79 maxItems: 1 80 81 clocks: 82 description: | 83 Several clocks are used, depending on the variant. Typical ones are:: 84 - cfg_noc:: System Config NOC clock. 85 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 86 60MHz for HS operation. 87 - iface:: System bus AXI clock. 88 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 89 power mode (U3). 90 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 91 mode. Its frequency should be 19.2MHz. 92 minItems: 1 93 maxItems: 9 94 95 clock-names: 96 minItems: 1 97 maxItems: 9 98 99 dma-coherent: true 100 101 iommus: 102 maxItems: 1 103 104 resets: 105 maxItems: 1 106 107 interconnects: 108 maxItems: 2 109 110 interconnect-names: 111 items: 112 - const: usb-ddr 113 - const: apps-usb 114 115 interrupts: 116 description: | 117 Different types of interrupts are used based on HS PHY used on target: 118 - dwc_usb3: Core DWC3 interrupt 119 - pwr_event: Used for wakeup based on other power events. 120 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 121 hs_phy_irq which is not triggered by default and its 122 functionality is mutually exclusive to that of 123 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 124 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 125 expose only a single IRQ whose behavior can be modified 126 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 127 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 128 of PHY address space. 129 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 130 DM pads of the SoC. These are used for wakeup 131 only on SoCs with non-QUSB2 targets with 132 exception of SDM670/SDM845/SM6350. 133 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 134 minItems: 3 135 maxItems: 19 136 137 interrupt-names: 138 minItems: 3 139 maxItems: 19 140 141 qcom,select-utmi-as-pipe-clk: 142 description: 143 If present, disable USB3 pipe_clk requirement. 144 Used when dwc3 operates without SSPHY and only 145 HS/FS/LS modes are supported. 146 type: boolean 147 148 wakeup-source: true 149 150# Required child node: 151 152required: 153 - compatible 154 - reg 155 - clocks 156 - clock-names 157 - interrupts 158 - interrupt-names 159 160allOf: 161 - $ref: snps,dwc3-common.yaml# 162 - if: 163 properties: 164 compatible: 165 contains: 166 enum: 167 - qcom,ipq4019-dwc3 168 - qcom,ipq5332-dwc3 169 then: 170 properties: 171 clocks: 172 maxItems: 3 173 clock-names: 174 items: 175 - const: core 176 - const: sleep 177 - const: mock_utmi 178 179 - if: 180 properties: 181 compatible: 182 contains: 183 enum: 184 - qcom,ipq8064-dwc3 185 then: 186 properties: 187 clocks: 188 items: 189 - description: Master/Core clock, has to be >= 125 MHz 190 for SS operation and >= 60MHz for HS operation. 191 clock-names: 192 items: 193 - const: core 194 195 - if: 196 properties: 197 compatible: 198 contains: 199 enum: 200 - qcom,ipq9574-dwc3 201 - qcom,msm8953-dwc3 202 - qcom,msm8996-dwc3 203 - qcom,msm8998-dwc3 204 - qcom,qcs8300-dwc3 205 - qcom,sa8775p-dwc3 206 - qcom,sc7180-dwc3 207 - qcom,sc7280-dwc3 208 - qcom,sdm670-dwc3 209 - qcom,sdm845-dwc3 210 - qcom,sdx55-dwc3 211 - qcom,sdx65-dwc3 212 - qcom,sdx75-dwc3 213 - qcom,sm6350-dwc3 214 then: 215 properties: 216 clocks: 217 maxItems: 5 218 clock-names: 219 items: 220 - const: cfg_noc 221 - const: core 222 - const: iface 223 - const: sleep 224 - const: mock_utmi 225 226 - if: 227 properties: 228 compatible: 229 contains: 230 enum: 231 - qcom,ipq6018-dwc3 232 then: 233 properties: 234 clocks: 235 minItems: 3 236 maxItems: 4 237 clock-names: 238 oneOf: 239 - items: 240 - const: core 241 - const: sleep 242 - const: mock_utmi 243 - items: 244 - const: cfg_noc 245 - const: core 246 - const: sleep 247 - const: mock_utmi 248 249 - if: 250 properties: 251 compatible: 252 contains: 253 enum: 254 - qcom,ipq8074-dwc3 255 - qcom,qdu1000-dwc3 256 then: 257 properties: 258 clocks: 259 maxItems: 4 260 clock-names: 261 items: 262 - const: cfg_noc 263 - const: core 264 - const: sleep 265 - const: mock_utmi 266 267 - if: 268 properties: 269 compatible: 270 contains: 271 enum: 272 - qcom,ipq5018-dwc3 273 - qcom,msm8994-dwc3 274 - qcom,qcs404-dwc3 275 then: 276 properties: 277 clocks: 278 maxItems: 4 279 clock-names: 280 items: 281 - const: core 282 - const: iface 283 - const: sleep 284 - const: mock_utmi 285 286 - if: 287 properties: 288 compatible: 289 contains: 290 enum: 291 - qcom,sc8280xp-dwc3 292 - qcom,sc8280xp-dwc3-mp 293 - qcom,x1e80100-dwc3 294 - qcom,x1e80100-dwc3-mp 295 then: 296 properties: 297 clocks: 298 maxItems: 9 299 clock-names: 300 items: 301 - const: cfg_noc 302 - const: core 303 - const: iface 304 - const: sleep 305 - const: mock_utmi 306 - const: noc_aggr 307 - const: noc_aggr_north 308 - const: noc_aggr_south 309 - const: noc_sys 310 311 - if: 312 properties: 313 compatible: 314 contains: 315 enum: 316 - qcom,sdm660-dwc3 317 then: 318 properties: 319 clocks: 320 minItems: 4 321 maxItems: 5 322 clock-names: 323 oneOf: 324 - items: 325 - const: cfg_noc 326 - const: core 327 - const: iface 328 - const: sleep 329 - const: mock_utmi 330 - items: 331 - const: cfg_noc 332 - const: core 333 - const: sleep 334 - const: mock_utmi 335 336 - if: 337 properties: 338 compatible: 339 contains: 340 enum: 341 - qcom,qcm2290-dwc3 342 - qcom,qcs615-dwc3 343 - qcom,sar2130p-dwc3 344 - qcom,sc8180x-dwc3 345 - qcom,sc8180x-dwc3-mp 346 - qcom,sm6115-dwc3 347 - qcom,sm6125-dwc3 348 - qcom,sm8150-dwc3 349 - qcom,sm8250-dwc3 350 - qcom,sm8450-dwc3 351 - qcom,sm8550-dwc3 352 - qcom,sm8650-dwc3 353 then: 354 properties: 355 clocks: 356 minItems: 6 357 clock-names: 358 items: 359 - const: cfg_noc 360 - const: core 361 - const: iface 362 - const: sleep 363 - const: mock_utmi 364 - const: xo 365 366 - if: 367 properties: 368 compatible: 369 contains: 370 enum: 371 - qcom,sm8350-dwc3 372 then: 373 properties: 374 clocks: 375 minItems: 5 376 maxItems: 6 377 clock-names: 378 minItems: 5 379 items: 380 - const: cfg_noc 381 - const: core 382 - const: iface 383 - const: sleep 384 - const: mock_utmi 385 - const: xo 386 387 - if: 388 properties: 389 compatible: 390 contains: 391 enum: 392 - qcom,ipq5018-dwc3 393 - qcom,ipq6018-dwc3 394 - qcom,ipq8074-dwc3 395 - qcom,msm8953-dwc3 396 - qcom,msm8998-dwc3 397 then: 398 properties: 399 interrupts: 400 minItems: 3 401 maxItems: 4 402 interrupt-names: 403 minItems: 3 404 items: 405 - const: dwc_usb3 406 - const: pwr_event 407 - const: qusb2_phy 408 - const: ss_phy_irq 409 410 - if: 411 properties: 412 compatible: 413 contains: 414 enum: 415 - qcom,msm8996-dwc3 416 - qcom,qcs404-dwc3 417 - qcom,sdm660-dwc3 418 - qcom,sm6115-dwc3 419 - qcom,sm6125-dwc3 420 then: 421 properties: 422 interrupts: 423 minItems: 4 424 maxItems: 5 425 interrupt-names: 426 minItems: 4 427 items: 428 - const: dwc_usb3 429 - const: pwr_event 430 - const: qusb2_phy 431 - const: hs_phy_irq 432 - const: ss_phy_irq 433 434 - if: 435 properties: 436 compatible: 437 contains: 438 enum: 439 - qcom,ipq5332-dwc3 440 then: 441 properties: 442 interrupts: 443 maxItems: 4 444 interrupt-names: 445 items: 446 - const: dwc_usb3 447 - const: pwr_event 448 - const: dp_hs_phy_irq 449 - const: dm_hs_phy_irq 450 451 - if: 452 properties: 453 compatible: 454 contains: 455 enum: 456 - qcom,x1e80100-dwc3 457 then: 458 properties: 459 interrupts: 460 maxItems: 5 461 interrupt-names: 462 items: 463 - const: dwc_usb3 464 - const: pwr_event 465 - const: dp_hs_phy_irq 466 - const: dm_hs_phy_irq 467 - const: ss_phy_irq 468 469 - if: 470 properties: 471 compatible: 472 contains: 473 enum: 474 - qcom,ipq4019-dwc3 475 - qcom,ipq8064-dwc3 476 - qcom,msm8994-dwc3 477 - qcom,qcs615-dwc3 478 - qcom,qcs8300-dwc3 479 - qcom,qdu1000-dwc3 480 - qcom,sa8775p-dwc3 481 - qcom,sc7180-dwc3 482 - qcom,sc7280-dwc3 483 - qcom,sc8180x-dwc3 484 - qcom,sc8280xp-dwc3 485 - qcom,sdm670-dwc3 486 - qcom,sdm845-dwc3 487 - qcom,sdx55-dwc3 488 - qcom,sdx65-dwc3 489 - qcom,sdx75-dwc3 490 - qcom,sm4250-dwc3 491 - qcom,sm6350-dwc3 492 - qcom,sm8150-dwc3 493 - qcom,sm8250-dwc3 494 - qcom,sm8350-dwc3 495 - qcom,sm8450-dwc3 496 - qcom,sm8550-dwc3 497 - qcom,sm8650-dwc3 498 then: 499 properties: 500 interrupts: 501 minItems: 5 502 maxItems: 6 503 interrupt-names: 504 minItems: 5 505 items: 506 - const: dwc_usb3 507 - const: pwr_event 508 - const: hs_phy_irq 509 - const: dp_hs_phy_irq 510 - const: dm_hs_phy_irq 511 - const: ss_phy_irq 512 513 - if: 514 properties: 515 compatible: 516 contains: 517 enum: 518 - qcom,sc8180x-dwc3-mp 519 - qcom,x1e80100-dwc3-mp 520 then: 521 properties: 522 interrupts: 523 minItems: 11 524 maxItems: 11 525 interrupt-names: 526 items: 527 - const: dwc_usb3 528 - const: pwr_event_1 529 - const: pwr_event_2 530 - const: hs_phy_1 531 - const: hs_phy_2 532 - const: dp_hs_phy_1 533 - const: dm_hs_phy_1 534 - const: dp_hs_phy_2 535 - const: dm_hs_phy_2 536 - const: ss_phy_1 537 - const: ss_phy_2 538 539 - if: 540 properties: 541 compatible: 542 contains: 543 enum: 544 - qcom,sc8280xp-dwc3-mp 545 then: 546 properties: 547 interrupts: 548 minItems: 19 549 maxItems: 19 550 interrupt-names: 551 items: 552 - const: dwc_usb3 553 - const: pwr_event_1 554 - const: pwr_event_2 555 - const: pwr_event_3 556 - const: pwr_event_4 557 - const: hs_phy_1 558 - const: hs_phy_2 559 - const: hs_phy_3 560 - const: hs_phy_4 561 - const: dp_hs_phy_1 562 - const: dm_hs_phy_1 563 - const: dp_hs_phy_2 564 - const: dm_hs_phy_2 565 - const: dp_hs_phy_3 566 - const: dm_hs_phy_3 567 - const: dp_hs_phy_4 568 - const: dm_hs_phy_4 569 - const: ss_phy_1 570 - const: ss_phy_2 571 572unevaluatedProperties: false 573 574examples: 575 - | 576 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 577 #include <dt-bindings/interrupt-controller/arm-gic.h> 578 #include <dt-bindings/interrupt-controller/irq.h> 579 soc { 580 #address-cells = <2>; 581 #size-cells = <2>; 582 583 usb@a600000 { 584 compatible = "qcom,sdm845-dwc3", "qcom,snps-dwc3"; 585 reg = <0 0x0a600000 0 0x100000>; 586 587 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 588 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 589 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 590 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 591 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 592 clock-names = "cfg_noc", 593 "core", 594 "iface", 595 "sleep", 596 "mock_utmi"; 597 598 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 599 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 600 assigned-clock-rates = <19200000>, <150000000>; 601 602 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 606 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 607 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 608 interrupt-names = "dwc_usb3", "pwr_event", "hs_phy_irq", 609 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 610 611 power-domains = <&gcc USB30_PRIM_GDSC>; 612 613 resets = <&gcc GCC_USB30_PRIM_BCR>; 614 615 iommus = <&apps_smmu 0x740 0>; 616 snps,dis_u2_susphy_quirk; 617 snps,dis_enblslpm_quirk; 618 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 619 phy-names = "usb2-phy", "usb3-phy"; 620 }; 621 }; 622... 623