Lines Matching +full:hs +full:- +full:usb +full:- +full:if
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
10 - Wesley Cheng <quic_wcheng@quicinc.com>
15 - enum:
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq6018-dwc3
20 - qcom,ipq8064-dwc3
21 - qcom,ipq8074-dwc3
22 - qcom,ipq9574-dwc3
23 - qcom,msm8953-dwc3
24 - qcom,msm8994-dwc3
25 - qcom,msm8996-dwc3
26 - qcom,msm8998-dwc3
27 - qcom,qcm2290-dwc3
28 - qcom,qcs404-dwc3
29 - qcom,qdu1000-dwc3
30 - qcom,sa8775p-dwc3
31 - qcom,sc7180-dwc3
32 - qcom,sc7280-dwc3
33 - qcom,sc8180x-dwc3
34 - qcom,sc8180x-dwc3-mp
35 - qcom,sc8280xp-dwc3
36 - qcom,sc8280xp-dwc3-mp
37 - qcom,sdm660-dwc3
38 - qcom,sdm670-dwc3
39 - qcom,sdm845-dwc3
40 - qcom,sdx55-dwc3
41 - qcom,sdx65-dwc3
42 - qcom,sdx75-dwc3
43 - qcom,sm4250-dwc3
44 - qcom,sm6115-dwc3
45 - qcom,sm6125-dwc3
46 - qcom,sm6350-dwc3
47 - qcom,sm6375-dwc3
48 - qcom,sm8150-dwc3
49 - qcom,sm8250-dwc3
50 - qcom,sm8350-dwc3
51 - qcom,sm8450-dwc3
52 - qcom,sm8550-dwc3
53 - qcom,sm8650-dwc3
54 - qcom,x1e80100-dwc3
55 - qcom,x1e80100-dwc3-mp
56 - const: qcom,dwc3
62 "#address-cells":
65 "#size-cells":
70 power-domains:
74 required-opps:
80 - cfg_noc:: System Config NOC clock.
81 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >=
82 60MHz for HS operation.
83 - iface:: System bus AXI clock.
84 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low
86 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host
91 clock-names:
101 interconnect-names:
103 - const: usb-ddr
104 - const: apps-usb
108 Different types of interrupts are used based on HS PHY used on target:
109 - pwr_event: Used for wakeup based on other power events.
110 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is
114 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and
119 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/
121 only on SoCs with non-QUSB2 targets with
123 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation.
127 interrupt-names:
131 qcom,select-utmi-as-pipe-clk:
133 If present, disable USB3 pipe_clk requirement.
135 HS/FS/LS modes are supported.
138 wakeup-source: true
143 "^usb@[0-9a-f]+$":
148 wakeup-source: false
151 - compatible
152 - reg
153 - "#address-cells"
154 - "#size-cells"
155 - ranges
156 - clocks
157 - clock-names
158 - interrupts
159 - interrupt-names
162 - if:
167 - qcom,ipq4019-dwc3
168 - qcom,ipq5332-dwc3
173 clock-names:
175 - const: core
176 - const: sleep
177 - const: mock_utmi
179 - if:
184 - qcom,ipq8064-dwc3
189 - description: Master/Core clock, has to be >= 125 MHz
190 for SS operation and >= 60MHz for HS operation.
191 clock-names:
193 - const: core
195 - if:
200 - qcom,ipq9574-dwc3
201 - qcom,msm8953-dwc3
202 - qcom,msm8996-dwc3
203 - qcom,msm8998-dwc3
204 - qcom,sa8775p-dwc3
205 - qcom,sc7180-dwc3
206 - qcom,sc7280-dwc3
207 - qcom,sdm670-dwc3
208 - qcom,sdm845-dwc3
209 - qcom,sdx55-dwc3
210 - qcom,sdx65-dwc3
211 - qcom,sdx75-dwc3
212 - qcom,sm6350-dwc3
217 clock-names:
219 - const: cfg_noc
220 - const: core
221 - const: iface
222 - const: sleep
223 - const: mock_utmi
225 - if:
230 - qcom,ipq6018-dwc3
236 clock-names:
238 - items:
239 - const: core
240 - const: sleep
241 - const: mock_utmi
242 - items:
243 - const: cfg_noc
244 - const: core
245 - const: sleep
246 - const: mock_utmi
248 - if:
253 - qcom,ipq8074-dwc3
254 - qcom,qdu1000-dwc3
259 clock-names:
261 - const: cfg_noc
262 - const: core
263 - const: sleep
264 - const: mock_utmi
266 - if:
271 - qcom,ipq5018-dwc3
272 - qcom,msm8994-dwc3
273 - qcom,qcs404-dwc3
278 clock-names:
280 - const: core
281 - const: iface
282 - const: sleep
283 - const: mock_utmi
285 - if:
290 - qcom,sc8280xp-dwc3
291 - qcom,sc8280xp-dwc3-mp
292 - qcom,x1e80100-dwc3
293 - qcom,x1e80100-dwc3-mp
298 clock-names:
300 - const: cfg_noc
301 - const: core
302 - const: iface
303 - const: sleep
304 - const: mock_utmi
305 - const: noc_aggr
306 - const: noc_aggr_north
307 - const: noc_aggr_south
308 - const: noc_sys
310 - if:
315 - qcom,sdm660-dwc3
321 clock-names:
323 - items:
324 - const: cfg_noc
325 - const: core
326 - const: iface
327 - const: sleep
328 - const: mock_utmi
329 - items:
330 - const: cfg_noc
331 - const: core
332 - const: sleep
333 - const: mock_utmi
335 - if:
340 - qcom,qcm2290-dwc3
341 - qcom,sc8180x-dwc3
342 - qcom,sc8180x-dwc3-mp
343 - qcom,sm6115-dwc3
344 - qcom,sm6125-dwc3
345 - qcom,sm8150-dwc3
346 - qcom,sm8250-dwc3
347 - qcom,sm8450-dwc3
348 - qcom,sm8550-dwc3
349 - qcom,sm8650-dwc3
354 clock-names:
356 - const: cfg_noc
357 - const: core
358 - const: iface
359 - const: sleep
360 - const: mock_utmi
361 - const: xo
363 - if:
368 - qcom,sm8350-dwc3
374 clock-names:
377 - const: cfg_noc
378 - const: core
379 - const: iface
380 - const: sleep
381 - const: mock_utmi
382 - const: xo
384 - if:
389 - qcom,ipq5018-dwc3
390 - qcom,ipq6018-dwc3
391 - qcom,ipq8074-dwc3
392 - qcom,msm8953-dwc3
393 - qcom,msm8998-dwc3
399 interrupt-names:
401 - const: pwr_event
402 - const: qusb2_phy
403 - const: ss_phy_irq
405 - if:
410 - qcom,msm8996-dwc3
411 - qcom,qcs404-dwc3
412 - qcom,sdm660-dwc3
413 - qcom,sm6115-dwc3
414 - qcom,sm6125-dwc3
420 interrupt-names:
422 - const: pwr_event
423 - const: qusb2_phy
424 - const: hs_phy_irq
425 - const: ss_phy_irq
427 - if:
432 - qcom,ipq5332-dwc3
437 interrupt-names:
439 - const: pwr_event
440 - const: dp_hs_phy_irq
441 - const: dm_hs_phy_irq
443 - if:
448 - qcom,x1e80100-dwc3
453 interrupt-names:
455 - const: pwr_event
456 - const: dp_hs_phy_irq
457 - const: dm_hs_phy_irq
458 - const: ss_phy_irq
460 - if:
465 - qcom,ipq4019-dwc3
466 - qcom,ipq8064-dwc3
467 - qcom,msm8994-dwc3
468 - qcom,qdu1000-dwc3
469 - qcom,sa8775p-dwc3
470 - qcom,sc7180-dwc3
471 - qcom,sc7280-dwc3
472 - qcom,sc8180x-dwc3
473 - qcom,sc8280xp-dwc3
474 - qcom,sdm670-dwc3
475 - qcom,sdm845-dwc3
476 - qcom,sdx55-dwc3
477 - qcom,sdx65-dwc3
478 - qcom,sdx75-dwc3
479 - qcom,sm4250-dwc3
480 - qcom,sm6350-dwc3
481 - qcom,sm8150-dwc3
482 - qcom,sm8250-dwc3
483 - qcom,sm8350-dwc3
484 - qcom,sm8450-dwc3
485 - qcom,sm8550-dwc3
486 - qcom,sm8650-dwc3
492 interrupt-names:
494 - const: pwr_event
495 - const: hs_phy_irq
496 - const: dp_hs_phy_irq
497 - const: dm_hs_phy_irq
498 - const: ss_phy_irq
500 - if:
505 - qcom,sc8180x-dwc3-mp
506 - qcom,x1e80100-dwc3-mp
512 interrupt-names:
514 - const: pwr_event_1
515 - const: pwr_event_2
516 - const: hs_phy_1
517 - const: hs_phy_2
518 - const: dp_hs_phy_1
519 - const: dm_hs_phy_1
520 - const: dp_hs_phy_2
521 - const: dm_hs_phy_2
522 - const: ss_phy_1
523 - const: ss_phy_2
525 - if:
530 - qcom,sc8280xp-dwc3-mp
536 interrupt-names:
538 - const: pwr_event_1
539 - const: pwr_event_2
540 - const: pwr_event_3
541 - const: pwr_event_4
542 - const: hs_phy_1
543 - const: hs_phy_2
544 - const: hs_phy_3
545 - const: hs_phy_4
546 - const: dp_hs_phy_1
547 - const: dm_hs_phy_1
548 - const: dp_hs_phy_2
549 - const: dm_hs_phy_2
550 - const: dp_hs_phy_3
551 - const: dm_hs_phy_3
552 - const: dp_hs_phy_4
553 - const: dm_hs_phy_4
554 - const: ss_phy_1
555 - const: ss_phy_2
560 - |
561 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
562 #include <dt-bindings/interrupt-controller/arm-gic.h>
563 #include <dt-bindings/interrupt-controller/irq.h>
565 #address-cells = <2>;
566 #size-cells = <2>;
568 usb@a6f8800 {
569 compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
572 #address-cells = <2>;
573 #size-cells = <2>;
580 clock-names = "cfg_noc",
586 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
588 assigned-clock-rates = <19200000>, <150000000>;
595 interrupt-names = "pwr_event", "hs_phy_irq",
598 power-domains = <&gcc USB30_PRIM_GDSC>;
602 usb@a600000 {
610 phy-names = "usb2-phy", "usb3-phy";