Lines Matching +full:hs +full:- +full:usb +full:- +full:if
1 /* SPDX-License-Identifier: GPL-2.0 */
11 * Copyright (c) 2003-2010 Cavium Networks (support@cavium.com). All rights
41 * SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
104 * This register can be used to configure the core after power-on or a change in
105 * mode of operation. This register mainly contains AHB system-related
106 * configuration parameters. The AHB is the processor interface to the O2P USB
110 * The application must program this register as part of the O2P USB core
126 * @nptxfemplvl: Non-Periodic TxFIFO Empty Level (NPTxFEmpLvl)
128 * Indicates when the Non-Periodic TxFIFO Empty Interrupt bit in
131 * * 1'b0: GINTSTS.NPTxFEmp interrupt indicates that the Non-
133 * * 1'b1: GINTSTS.NPTxFEmp interrupt indicates that the Non-
165 * This register contains the configuration options of the O2P USB core.
172 * This value is in terms of 32-bit words.
195 * The application uses this bit to indicate the O2P USB core's
211 * - ...
267 * @usbrstmsk: USB Reset Mask (USBRstMsk)
268 * @usbsuspmsk: USB Suspend Mask (USBSuspMsk)
274 * @ginnakeffmsk: Global Non-Periodic IN NAK Effective Mask
276 * @nptxfempmsk: Non-Periodic TxFIFO Empty Mask (NPTxFEmpMsk)
277 * @rxflvlmsk: Receive FIFO Non-Empty Mask (RxFLvlMsk)
324 * This register interrupts the application for system-level events in the
340 * detected on the USB. In Host mode, this interrupt is asserted
341 * when a remote wakeup is detected on the USB.
343 * Power-Down and Clock Gating Programming Model" on
351 * Power-Down and Clock Gating Programming Model" on
371 * Channel-n Interrupt (HCINTn) register to determine the exact
376 * one of the O2P USB core ports in Host mode. The application must
409 * corresponding Device OUT Endpoint-n Interrupt (DOEPINTn)
419 * corresponding Device IN Endpoint-n Interrupt (DIEPINTn)
424 * Indicates that an IN token has been received for a non-periodic
426 * top of the Non-Periodic Transmit FIFO and the IN endpoint
441 * @usbrst: USB Reset (USBRst)
443 * the USB.
444 * @usbsusp: USB Suspend (USBSusp)
446 * on the USB. The core enters the Suspended state when there
451 * detected on the USB for 3 ms.
462 * @ginnakeff: Global IN Non-Periodic NAK Effective (GINNakEff)
463 * Indicates that the Set Global Non-Periodic IN NAK bit in the
467 * can be cleared by clearing the Clear Global Non-Periodic IN
470 * is sent out on the USB. The STALL bit takes precedence over
472 * @nptxfemp: Non-Periodic TxFIFO Empty (NPTxFEmp)
473 * This interrupt is asserted when the Non-Periodic TxFIFO is
475 * one entry to be written to the Non-Periodic Transmit Request
477 * the Non-Periodic TxFIFO Empty Level bit in the Core AHB
479 * @rxflvl: RxFIFO Non-Empty (RxFLvl)
484 * (FS), micro-SOF (HS), or Keep-Alive (LS) is transmitted on the
485 * USB. The application must write a 1 to this bit to clear the
488 * SOF token has been received on the USB. The application can read
491 * at either HS or FS.
552 * Non-Periodic Transmit FIFO Size Register (GNPTXFSIZ)
555 * Non-Periodic TxFIFO.
561 * @nptxfdep: Non-Periodic TxFIFO Depth (NPTxFDep)
562 * This value is in terms of 32-bit words.
565 * @nptxfstaddr: Non-Periodic Transmit RAM Start Address (NPTxFStAddr)
566 * This field contains the memory start address for Non-Periodic
579 * Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS)
581 * This read-only register contains the free space information for the
582 * Non-Periodic TxFIFO and the Non-Periodic Transmit Request Queue.
588 * @nptxqtop: Top of the Non-Periodic Transmit Request Queue (NPTxQTop)
589 * Entry in the Non-Periodic Tx Request Queue that is currently
593 * - 2'b00: IN/OUT token
594 * - 2'b01: Zero-length transmit packet (device IN/host OUT)
595 * - 2'b10: PING/CSPLIT token
596 * - 2'b11: Channel halt command
598 * @nptxqspcavail: Non-Periodic Transmit Request Queue Space Available
600 * Indicates the amount of free space available in the Non-
604 * * 8'h0: Non-Periodic Transmit Request Queue is full
609 * @nptxfspcavail: Non-Periodic TxFIFO Space Avail (NPTxFSpcAvail)
610 * Indicates the amount of free space available in the Non-
612 * Values are in terms of 32-bit words.
613 * * 16'h0: Non-Periodic TxFIFO is full
650 * * 5'h0: Non-Periodic TxFIFO flush
654 * - ...
656 * * 5'h10: Flush all the Periodic and Non-Periodic TxFIFOs in the
660 * cannot do so if the core is in the midst of a transaction.
700 * This is a self-clearing bit that the core clears after all
707 * - PCGCCTL.RstPdwnModule
708 * - PCGCCTL.GateHclk
709 * - PCGCCTL.PwrClmp
710 * - PCGCCTL.StopPPhyLPwrClkSelclk
711 * - GUSBCFG.PhyLPwrClkSel
712 * - GUSBCFG.DDRSel
713 * - GUSBCFG.PHYSel
714 * - GUSBCFG.FSIntf
715 * - GUSBCFG.ULPI_UTMI_Sel
716 * - GUSBCFG.PHYIf
717 * - HCFG.FSLSPclkSel
718 * - DCFG.DevSpd
724 * an AHB transfer. Any transactions on the USB are terminated
727 * the core. This is a self-clearing bit and the core clears this
737 * in the USB configuration registers listed above. When you
770 * This value is in terms of 32-bit words.
791 * same offset in the O2P USB core. The offset difference shown in this
830 * Core USB Configuration Register (GUSBCFG)
832 * This register can be used to configure the core after power-on or a changing
833 * to Host mode or Device mode. It contains USB and USB-PHY related
835 * starting any transactions on either the AHB or the USB. Do not make changes
844 * @phylpwrclksel: PHY Low-Power Clock Select (PhyLPwrClkSel)
846 * Selects either 480-MHz or 48-MHz (low-power) PHY mode. In
847 * FS and LS modes, the PHY can usually operate on a 48-MHz
849 * * 1'b0: 480-MHz Internal PLL clock
850 * * 1'b1: 48-MHz External Clock
852 * 30-MHz, depending upon whether 8- or 16-bit data width is
853 * selected. In 48-MHz mode, the UTMI interface operates at 48
858 * @usbtrdtim: USB Turnaround Time (USBTrdTim)
863 * @hnpcap: HNP-Capable (HNPCap)
865 * @srpcap: SRP-Capable (SRPCap)
869 * @physel: USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial
871 * @fsintf: Full-Speed Serial Interface Select (FSIntf)
877 * @toutcal: HS/FS Timeout Calibration (TOutCal)
879 * field is added to the high-speed/full-speed interpacket timeout
884 * The USB standard timeout value for high-speed operation is
885 * 736 to 816 (inclusive) bit times. The USB standard timeout
886 * value for full-speed operation is 16 to 18 (inclusive) bit
890 * High-speed operation:
891 * * One 30-MHz PHY clock = 16 bit times
892 * * One 60-MHz PHY clock = 8 bit times
893 * Full-speed operation:
894 * * One 30-MHz PHY clock = 0.4 bit times
895 * * One 60-MHz PHY clock = 0.2 bit times
896 * * One 48-MHz PHY clock = 0.25 bit times
926 * in the corresponding Host Channel-n Interrupt register.
970 * Host Channel-n Characteristics Register (HCCHAR)
998 * When the Split Enable bit of the Host Channel-n Split Control
1018 * @lspddev: Low-Speed Device (LSpdDev)
1020 * channel is communicating to a low-speed device.
1052 * This register configures the core after power-on. Do not make changes to this
1059 * @fslssupp: FS- and LS-Only Support (FSLSSupp)
1062 * enumerate as a FS host, even if the connected device supports
1063 * HS traffic. Do not make changes to this field after initial
1065 * * 1'b0: HS/FS/LS, based on the maximum speed supported by
1067 * * 1'b1: FS/LS-only, even if the connected device can support HS
1078 * PHY Low Power mode is selected, use 48MHz if the PHY
1080 * * 2'b10: PHY clock is running at 6 MHz. In USB 1.1 FS mode,
1083 * mode. If you select a 6 MHz clock during LS mode, you must
1098 * Host Channel-n Interrupt Register (HCINT)
1100 * This register indicates the status of a channel with respect to USB- and
1101 * AHB-related events. The application must read this register when the Host
1105 * number for the Host Channel-n Interrupt register. The application must clear
1124 * any USB transaction error or in response to disable request by
1149 * Host Channel-n Interrupt Mask Register (HCINTMSKn)
1191 * Host Channel-n Split Control Register (HCSPLT)
1236 * Host Channel-n Transfer Size Register (HCTSIZ)
1252 * * 2'b11: MDATA (non-control)/SETUP (control)
1266 * size for IN transactions (periodic and non-periodic).
1283 * which the O2P USB core has enumerated.
1291 * the interval between two consecutive SOFs (FS) or micro-
1292 * SOFs (HS) or Keep-Alive tokens (HS). This field contains the
1298 * has been set. If no value is programmed, the core calculates
1303 * * 125 us (PHY clock frequency for HS)
1328 * microframe (HS) or frame (FS/LS), in terms of PHY clocks.
1331 * Interval register and a new SOF is transmitted on the USB.
1334 * USB, and is reset to 0 when it reaches 16'h3FFF.
1350 * A single register holds USB port-related information such as USB reset,
1379 * PrtSpd must be zero (i.e. the interface must be in high-speed
1387 * Indicates the current logic level USB data lines
1388 * * Bit [10]: Logic level of D-
1402 * USB standard.
1425 * If the core detects a USB remote wakeup sequence, as
1497 * This value is in terms of 32-bit words.
1514 * This read-only register contains the free space information for the Periodic
1526 * - 1'b0: send in even (micro)frame
1527 * - 1'b1: send in odd (micro)frame
1530 * - 2'b00: IN/OUT
1531 * - 2'b01: Zero-length packet
1532 * - 2'b10: CSPLIT
1533 * - 2'b11: Disable channel command
1550 * Values are in terms of 32-bit words
1578 * @divide2: The 'hclk' used by the USB subsystem is derived
1585 * @hclk_rst: When this field is '0' the HCLK-DIVIDER used to
1586 * generate the hclk in the USB Subsystem is held
1591 * @p_x_on: Force USB-PHY on during suspend.
1592 * '1' USB-PHY XO block is powered-down during
1594 * '0' USB-PHY XO block is powered-up during
1600 * '0' The USB-PHY uses a 12MHz crystal as a clock source
1615 * @p_com_on: '0' Force USB-PHY XO Bias, Bandgap and PLL to
1617 * '1' The USB-PHY XO Bias, Bandgap and PLL are
1629 * NOTE: if a crystal is used as a reference clock,
1642 * the phy_clk functionality in the USB Subsystem is
1649 * the hclk functioanlity in the USB Subsystem is
1654 * @divide: The frequency of 'hclk' used by the USB subsystem
1695 * @txrisetune: HS Transmitter Rise/Fall Time Adjustment
1696 * @txvreftune: HS DC Voltage Level Adjustment
1698 * @txhsxvtune: Transmitter High-Speed Crossover Adjustment
1705 * @lsbist: Low-Speed BIST Enable.
1706 * @fsbist: Full-Speed BIST Enable.
1707 * @hsbist: High-Speed BIST Enable.
1717 * @siddq: Drives the USBP (USB-PHY) SIDDQ input.
1719 * When customers have no intent to use USB PHY
1721 * - still provide 3.3V to USB_VDD33, and
1722 * - tie USB_REXT to 3.3V supply, and
1723 * - set USBN*_USBP_CTL_STATUS[SIDDQ]=1
1724 * @txpreemphasistune: HS Transmitter Pre-Emphasis Enable
1726 * with byte-counts between packets. When set to 0
1728 * 4-byte aligned address after adding byte-count.
1729 * @usbc_end: Bigendian input to the USB Core. This should be
1733 * @dp_pulld: PHY DP_PULLDOWN input to the USB-PHY.
1734 * This signal enables the pull-down resistance on
1735 * the D+ line. '1' pull down-resistance is connected
1738 * (downstream-facing port), dp_pulldown and
1741 * @dm_pulld: PHY DM_PULLDOWN input to the USB-PHY.
1742 * This signal enables the pull-down resistance on
1743 * the D- line. '1' pull down-resistance is connected
1744 * to D-. '0' pull down resistance is not connected
1745 * to D-. When an A/B device is acting as a host
1746 * (downstream-facing port), dp_pulldown and
1749 * @hst_mode: When '0' the USB is acting as HOST, when '1'
1750 * USB is acting as device. This field needs to be
1751 * set while the USB is in reset.
1752 * @tuning: Transmitter Tuning for High-Speed Operation.
1754 * times for high-speed operation.
1769 * when bit-stuffing is enabled.
1772 * when bit-stuffing is enabled.
1783 * @bist_enb: Built-In Self Test Enable.
1797 * This is a test signal. When the USB Core is
1800 * free_clk, then re-enable them with an aligned
1805 * de-assertion.