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/linux/drivers/net/ethernet/mellanox/mlx5/core/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 Core driver for low level functionality of the ConnectX-4 and
17 Connect-IB cards by Mellanox Technologies.
27 sandbox-specific client drivers.
36 Ethernet support in Mellanox Technologies ConnectX-4 NIC.
43 Mellanox MLX5 ethernet hardware-accelerated receive flow steering support,
61 Mellanox Technologies Ethernet Multi-Physical Function Switch (MPFS)
62 support in ConnectX NIC. MPFs is required for when multi-PF configuration
67 bool "Mellanox Technologies MLX5 SRIOV E-Switch support"
71 Mellanox Technologies Ethernet SRIOV E-Switch support in ConnectX NIC.
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/linux/drivers/clk/
H A Dclk_kunit_helpers.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/clk-provider.h>
17 * clk_prepare_enable_kunit() - Test managed clk_prepare_enable()
53 * clk_get_kunit() - Test managed clk_get()
58 * Just like clk_get(), except the clk is managed by the test case and is
75 * of_clk_get_kunit() - Test managed of_clk_get()
80 * Just like of_clk_get(), except the clk is managed by the test case and is
97 * clk_hw_get_clk_kunit() - Test managed clk_hw_get_clk()
102 * Just like clk_hw_get_clk(), except the clk is managed by the test case and
119 * clk_hw_get_clk_prepared_enabled_kunit() - Test managed clk_hw_get_clk() + clk_prepare_enable()
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/linux/drivers/cxl/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
27 The CXL specification defines a "CXL memory device" sub-class in the
30 memory to be mapped into the system address map (Host-managed Device
51 or by design. When prototyping new hardware, or developing / debugging
53 the hardware, even commands that may crash the kernel due to their
56 If developing CXL hardware or the driver say Y, otherwise say N.
68 Enable support for host managed device memory (HDM) resources
72 (https://www.computeexpresslink.org/spec-landing). The CXL core
75 Memory regions to be managed by LIBNVDIMM.
86 managed via a bridge driver from CXL to the LIBNVDIMM system
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/linux/include/drm/
H A Ddrm_device.h29 * Recovery methods for wedged device in order of less to more side-effects.
33 * Refer to "Device Wedging" chapter in Documentation/gpu/drm-uapi.rst for more
42 * struct drm_wedge_task_info - information about the guilty task of a wedge dev
52 * enum switch_power_state - power state of drm device
70 * struct drm_device - DRM device structure
79 /** @ref: Object ref-count */
82 /** @dev: Device structure of bus-device */
100 * for importing buffers via dma-buf.
108 * @managed:
110 * Managed resources linked to the lifetime of this &drm_device as
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/linux/Documentation/arch/x86/
H A Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
31 Shared Hardware Workqueues
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
36 Machines (VM's). This allows better hardware utilization vs. hard
38 allow the hardware to distinguish the context for which work is being
39 executed in the hardware by SWQ interface, SIOV uses Process Address Space
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
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/linux/drivers/net/pse-pd/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
28 hardware on various Realtek-based managed switches, attached
29 via I2C/SMBus. The MCU exposes a message-based protocol; the actual
31 module, choose M here: the module will be called realtek-pse-mcu-i2c.
39 hardware on various Realtek-based managed switches, attached
40 via UART. The MCU exposes a message-based protocol; the actual PSE
42 module, choose M here: the module will be called realtek-pse-mcu-uart.
69 Only 4-pair PSE configurations are supported.
/linux/Documentation/devicetree/bindings/net/
H A Dqcom,ipq9574-ppe.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Luo Jie <jie.luo@oss.qualcomm.com>
11 - Lei Wei <quic_leiwei@quicinc.com>
12 - Suruchi Agarwal <quic_suruchia@quicinc.com>
13 - Pavithra R <quic_pavir@quicinc.com>
28 supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There
34 The follow diagram shows the PPE hardware block along with its connectivity
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/linux/Documentation/ABI/testing/
H A Dsysfs-driver-intel-m10-bmc1 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmc_version
5 Description: Read only. Returns the hardware build version of Intel
9 What: /sys/bus/.../drivers/intel-m10-bmc/.../bmcfw_version
17 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_address
23 that is managed by the Intel MAX10 BMC. It is stored in
28 What: /sys/bus/.../drivers/intel-m10-bmc/.../mac_count
33 addresses assigned to the board managed by the Intel
/linux/Documentation/userspace-api/
H A Diommufd.rst1 .. SPDX-License-Identifier: GPL-2.0+
20 I/O page tables for all IOMMUs, with room in the design to add non-generic
21 features to cater to specific hardware functionality.
31 --------------------
35 - IOMMUFD_OBJ_IOAS, representing an I/O address space (IOAS), allowing map/unmap
41 - IOMMUFD_OBJ_DEVICE, representing a device that is bound to iommufd by an
44 - IOMMUFD_OBJ_HWPT_PAGING, representing an actual hardware I/O page table
45 (i.e. a single struct iommu_domain) managed by the iommu driver. "PAGING"
48 feature flag. This can be either an UNMANAGED stage-1 domain for a device
49 running in the user space, or a nesting parent stage-2 domain for mappings
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/linux/Documentation/driver-api/driver-model/
H A Ddevres.rst2 Devres - Managed Device Resource
16 6. List of managed interfaces: Currently implemented managed interfaces
20 --------
29 sufficient bugs in ->remove and ->probe failure path. Well, yes,
32 day fiddling with braindamaged hardware with no document or
42 and having half broken failure path implementation in ->probe() which
48 ---------
57 Managed interface is created for resources commonly used by device
59 using dma_alloc_coherent(). The managed version is called
61 for the DMA memory allocated using it is managed and will be
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/linux/Documentation/devicetree/bindings/soc/ti/
H A Dkeystone-navigator-qmss.txt4 the main hardware sub system which forms the backbone of the Keystone
5 multi-core Navigator. QMSS consist of queue managers, packed-data structure
8 The Queue Manager is a hardware module that is responsible for accelerating
9 management of the packet queues. Packets are queued/de-queued by writing or
20 - compatible : Must be "ti,keystone-navigator-qmss".
21 : Must be "ti,66ak2g-navss-qm" for QMSS on K2G SoC.
22 - clocks : phandle to the reference clock for this device.
23 - queue-range : <start number> total range of queue numbers for the device.
24 - linkram0 : <address size> for internal link ram, where size is the total
26 - linkram1 : <address size> for external link ram, where size is the total
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/linux/arch/microblaze/include/asm/
H A Dmmu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
17 /* Hardware Page Table Entry */
27 unsigned long w:1; /* Write-thru cache mode */
46 unsigned long n:1; /* No-execute */
55 * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
62 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
63 * instruction and data sides share a unified, 64-entry, semi-associative
65 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
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/linux/include/linux/pse-pd/
H A Dpse.h1 // SPDX-License-Identifier: GPL-2.0-only
15 /* Maximum current in uA according to IEEE 802.3-2022 Table 145-1 */
17 /* Maximum power in mW according to IEEE 802.3-2022 Table 145-16 */
46 * struct pse_irq_desc - notification sender description for IRQ based events.
59 * struct pse_control_config - PSE control/channel configuration.
62 * IEEE 802.3-2018 30.15.1.2.1 acPoDLPSEAdminControl
64 * IEEE 802.3-2022 30.9.1.2.1 acPSEAdminControl
72 * struct pse_admin_state - PSE operational state
75 * functions. IEEE 802.3-2018 30.15.1.1.2 aPoDLPSEAdminState
77 * functions. IEEE 802.3-2022 30.9.1.1.2 aPSEAdminState
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/linux/include/uapi/linux/
H A Ddcbnl.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 2008-2011, Intel Corporation.
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
34 /* This structure contains the IEEE 802.1Qaz ETS managed object
48 * with hardware offloaded LLDP.
50 * ----
53 * 1 credit-based shaper
55 * 3-254 reserved
72 * managed object.
89 /* This structure contains the IEEE 802.1Qau QCN managed object.
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/linux/drivers/hwtracing/ptt/
H A Dhisi_ptt.h1 /* SPDX-License-Identifier: GPL-2.0 */
71 /* Wait time for hardware DMA to reset */
74 /* Poll timeout and interval for waiting hardware work to finish */
94 * struct hisi_ptt_tune_desc - Describe tune event for PTT tune
106 * struct hisi_ptt_dma_buffer - Describe a single trace buffer of PTT trace.
118 * struct hisi_ptt_trace_ctrl - Control and status of PTT trace
154 * struct hisi_ptt_filter_desc - Descriptor of the PTT trace filter
170 * struct hisi_ptt_filter_update_info - Information for PTT filter updating
182 * struct hisi_ptt_pmu_buf - Descriptor of the AUX buffer of PTT trace
196 * struct hisi_ptt - Per PTT device data
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/linux/Documentation/driver-api/gpio/
H A Dusing-gpio.rst5 The Linux kernel exists to abstract and present hardware to users. GPIO lines
7 and preferred way to use GPIO lines is to let kernel hardware drivers deal
12 Documentation/driver-api/gpio/drivers-on-gpio.rst
18 help to refine it, see Documentation/process/submitting-patches.rst.
22 The userspace ABI is intended for one-off deployments. Examples are prototypes,
24 industrial automation, PLC-type use cases, door controllers, in short a piece
27 software-hardware interface to be set up. They should not have a natural fit
30 computer hardware related policy.
41 The userspace ABI is a character device for each GPIO hardware unit (GPIO chip).
46 For structured and managed applications, we recommend that you make use of the
/linux/Documentation/driver-api/iio/
H A Dtriggers.rst6 * :c:func:`devm_iio_trigger_alloc` — Resource-managed iio_trigger_alloc
7 * :c:func:`devm_iio_trigger_register` — Resource-managed iio_trigger_register
15 based on hardware generated events (e.g. data ready or threshold exceeded) or
55 trig = iio_trigger_alloc(dev, "trig-%s-%d", name, idx);
58 trig->ops = &trigger_ops;
76 .. kernel-doc:: include/linux/iio/trigger.h
77 .. kernel-doc:: drivers/iio/industrialio-trigger.c
/linux/Documentation/arch/s390/
H A Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
8 - Pierre Morel
9 - Niklas Schnelle
18 -----------------------
29 ---------------
38 - /sys/kernel/debug/s390dbf/pci_msg/sprintf
59 - /sys/bus/pci/slots/XXXXXXXX/power
62 also contains the following s390-specific slot attributes.
64 - uid:
65 The User-defined identifier (UID) of the function which may be configured
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/linux/Documentation/devicetree/bindings/clock/
H A Dmediatek,mt8196-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guangjie Song <guangjie.song@mediatek.com>
11 - Laura Nao <laura.nao@collabora.com>
15 PLLs -->
16 dividers -->
18 -->
26 - enum:
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H A Dmediatek,mt8196-sys-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/mediatek,mt8196-sys-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Guangjie Song <guangjie.song@mediatek.com>
11 - Laura Nao <laura.nao@collabora.com>
15 PLLs -->
16 dividers -->
18 -->
29 - enum:
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/linux/net/mctp/
H A DKconfig6 Management Component Transport Protocol (MCTP) is an in-system
8 their managed devices (peripherals, host processors, etc.). The
12 devices, you'll want to enable a driver for a specific hardware
/linux/arch/x86/kernel/apic/
H A Dvector.c1 // SPDX-License-Identifier: GPL-2.0-only
78 info->mask = mask; in init_irq_alloc_info()
94 while (irqd->parent_data) in apic_chip_data()
95 irqd = irqd->parent_data; in apic_chip_data()
97 return irqd->chip_data; in apic_chip_data()
104 return apicd ? &apicd->hw_irq_cfg : NULL; in irqd_cfg()
119 INIT_HLIST_NODE(&apicd->clist); in alloc_apic_chip_data()
135 apicd->hw_irq_cfg.vector = vector; in apic_update_irq_cfg()
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
141 trace_vector_config(irqd->irq, vector, cpu, apicd->hw_irq_cfg.dest_apicid); in apic_update_irq_cfg()
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/linux/drivers/clk/bcm/
H A Dclk-kona.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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/linux/Documentation/networking/devlink/
H A Dmlx5.rst1 .. SPDX-License-Identifier: GPL-2.0
13 .. list-table:: Generic parameters implemented
15 * - Name
16 - Mode
17 - Validation
18 - Notes
19 * - ``enable_roce``
20 - driverinit
21 - Boolean
22 - If the device supports RoCE disablement, RoCE enablement state controls
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/linux/Documentation/admin-guide/pm/
H A Dintel_pstate.rst1 .. SPDX-License-Identifier: GPL-2.0
22 Documentation/admin-guide/pm/cpufreq.rst if you have not done that yet.]
24 For the processors supported by ``intel_pstate``, the P-state concept is broader
27 information about that). For this reason, the representation of P-states used
28 by ``intel_pstate`` internally follows the hardware specification (for details
32 ``intel_pstate`` maps its internal representation of P-states to frequencies too
38 Since the hardware P-state selection interface used by ``intel_pstate`` is
43 time the corresponding CPU is taken offline and need to be re-initialized when
47 only way to pass early-configuration-time parameters to it is via the kernel
60 allows the hardware to do performance scaling by itself, while in the passive
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