Lines Matching +full:hardware +full:- +full:managed
1 .. SPDX-License-Identifier: GPL-2.0
19 application page-faults. For more information please refer to the PCIe
31 Shared Hardware Workqueues
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
36 Machines (VM's). This allows better hardware utilization vs. hard
38 allow the hardware to distinguish the context for which work is being
39 executed in the hardware by SWQ interface, SIOV uses Process Address Space
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
55 ENQCMD works with non-posted semantics and carries a status back if the
56 command was accepted by hardware. This allows the submitter to know if the
61 to the hardware and also permits hardware to be aware of application context
67 A new thread-scoped MSR (IA32_PASID) provides the connection between
68 user processes and the rest of the hardware. When an application first
69 accesses an SVA-capable device, this MSR is initialized with a newly
70 allocated PASID. The driver for the device calls an IOMMU-specific API
71 that sets up the routing for DMA and page-requests.
76 - Allocate the PASID, and program the process page-table (%cr3 register) in the
78 - Register for mmu_notifier() to track any page-table invalidations to keep
79 the device TLB in sync. For example, when a page-table entry is invalidated,
86 This MSR is managed with the XSAVE feature set as "supervisor state" to
94 platform hardware. ENQCMD uses the PASID stored in this MSR to tag requests
96 ENQCMD instruction, the PASID field in the descriptor is auto-filled with the
110 PASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.
112 Only processes that access SVA-capable devices need to have a PASID
113 allocated. This allocation happens when a process opens/binds an SVA-capable
126 and returns so that the ENQCMD instruction is re-executed.
153 * Devices have a limited number (~10's to 1000's) of hardware workqueues.
154 The device driver manages allocating hardware workqueues.
155 * A single mmap() maps a single hardware workqueue as a "portal" and
162 which case they still share one device hardware workqueue.
163 * The single process-wide PASID is used by all threads to interact
165 thread or each thread<->device pair.
172 Shared Virtual Addressing (SVA) permits I/O hardware and the processor to
180 A Process Address Space ID (PASID) is a PCIe-defined Transaction Layer Packet
181 (TLP) prefix. A PASID is a 20-bit number allocated and managed by the OS.
186 Traditionally, in order for userspace applications to interact with hardware,
187 there is a separate hardware instance required per process. For example,
188 consider doorbells as a mechanism of informing hardware about work to process.
189 Each doorbell is required to be spaced 4k (or page-size) apart for process
190 isolation. This requires hardware to provision that space and reserve it in
192 hardware also manages the queue depth for Shared Work Queues (SWQ), and
200 the PCIe subsystem, much like how PCIe atomic operations are managed for
203 SWQ allows hardware to provision just a single address in the device. When
212 initialization of the hardware. User space only needs to worry about
215 * Is this the same as SR-IOV?
217 Single Root I/O Virtualization (SR-IOV) focuses on providing independent
218 hardware interfaces for virtualizing hardware. Hence, it's required to be
220 BARs, space for interrupts via MSI-X, its own register layout.
228 hardware to optimize device resource creation and can grow dynamically on
229 demand. SR-IOV creation and management is very static in nature. Consult
234 Creating PCIe SR-IOV type Virtual Functions (VF) is expensive. VFs require
235 duplicated hardware for PCI config space and interrupts such as MSI-X.
240 creates a software-defined device where all the configuration and control
253 When devices support SVA along with platform hardware such as IOMMU
258 Device TLB support - Device requests the IOMMU to lookup an address before
260 but there is no page allocated by the OS, IOMMU hardware returns that no
268 IOMMU works with the OS in managing consistency of page-tables with the
276 VT-D:
277 https://01.org/blogs/ashokraj/2018/recent-enhancements-intel-virtualization-technology-directed-i/o…
280 https://01.org/blogs/2019/assignable-interfaces-intel-scalable-i/o-virtualization-linux
283 …s://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-p…
286 https://software.intel.com/sites/default/files/341204-intel-data-streaming-accelerator-spec.pdf