14cdadfd5SDan Williams# SPDX-License-Identifier: GPL-2.0-only 24cdadfd5SDan Williamsmenuconfig CXL_BUS 34cdadfd5SDan Williams tristate "CXL (Compute Express Link) Devices Support" 44cdadfd5SDan Williams depends on PCI 59171dfcdSArnd Bergmann select FW_LOADER 69171dfcdSArnd Bergmann select FW_UPLOAD 73eddcc93SIra Weiny select PCI_DOE 8ad6f04c0SDave Jiang select FIRMWARE_TABLE 91b5695b0SMike Rapoport (Microsoft) select NUMA_KEEP_MEMINFO if NUMA_MEMBLKS 104cdadfd5SDan Williams help 114cdadfd5SDan Williams CXL is a bus that is electrically compatible with PCI Express, but 124cdadfd5SDan Williams layers three protocols on that signalling (CXL.io, CXL.cache, and 134cdadfd5SDan Williams CXL.mem). The CXL.cache protocol allows devices to hold cachelines 144cdadfd5SDan Williams locally, the CXL.mem protocol allows devices to be fully coherent 154cdadfd5SDan Williams memory targets, the CXL.io protocol is equivalent to PCI Express. 164cdadfd5SDan Williams Say 'y' to enable support for the configuration and management of 174cdadfd5SDan Williams devices supporting these protocols. 184cdadfd5SDan Williams 194cdadfd5SDan Williamsif CXL_BUS 204cdadfd5SDan Williams 2168cdd3d2SBen Widawskyconfig CXL_PCI 2268cdd3d2SBen Widawsky tristate "PCI manageability" 233feaa2d3SDan Williams default CXL_BUS 244cdadfd5SDan Williams help 2568cdd3d2SBen Widawsky The CXL specification defines a "CXL memory device" sub-class in the 2668cdd3d2SBen Widawsky PCI "memory controller" base class of devices. Device's identified by 2768cdd3d2SBen Widawsky this class code provide support for volatile and / or persistent 2868cdd3d2SBen Widawsky memory to be mapped into the system address map (Host-managed Device 2968cdd3d2SBen Widawsky Memory (HDM)). 304cdadfd5SDan Williams 3168cdd3d2SBen Widawsky Say 'y/m' to enable a driver that will attach to CXL memory expander 3268cdd3d2SBen Widawsky devices enumerated by the memory device class code for configuration 3368cdd3d2SBen Widawsky and management primarily via the mailbox interface. See Chapter 2.3 3468cdd3d2SBen Widawsky Type 3 CXL Device in the CXL 2.0 specification for more details. 354cdadfd5SDan Williams 364cdadfd5SDan Williams If unsure say 'm'. 3713237183SBen Widawsky 3813237183SBen Widawskyconfig CXL_MEM_RAW_COMMANDS 3913237183SBen Widawsky bool "RAW Command Interface for Memory Devices" 4068cdd3d2SBen Widawsky depends on CXL_PCI 4113237183SBen Widawsky help 4213237183SBen Widawsky Enable CXL RAW command interface. 4313237183SBen Widawsky 4413237183SBen Widawsky The CXL driver ioctl interface may assign a kernel ioctl command 4513237183SBen Widawsky number for each specification defined opcode. At any given point in 4613237183SBen Widawsky time the number of opcodes that the specification defines and a device 4713237183SBen Widawsky may implement may exceed the kernel's set of associated ioctl function 4813237183SBen Widawsky numbers. The mismatch is either by omission, specification is too new, 4913237183SBen Widawsky or by design. When prototyping new hardware, or developing / debugging 5013237183SBen Widawsky the driver it is useful to be able to submit any possible command to 5113237183SBen Widawsky the hardware, even commands that may crash the kernel due to their 5213237183SBen Widawsky potential impact to memory currently in use by the kernel. 5313237183SBen Widawsky 5413237183SBen Widawsky If developing CXL hardware or the driver say Y, otherwise say N. 554812be97SDan Williams 564812be97SDan Williamsconfig CXL_ACPI 574812be97SDan Williams tristate "CXL ACPI: Platform Support" 584812be97SDan Williams depends on ACPI 59ad6f04c0SDave Jiang depends on ACPI_NUMA 603feaa2d3SDan Williams default CXL_BUS 61f4ce1f76SDan Williams select ACPI_TABLE_LIB 62ad6f04c0SDave Jiang select ACPI_HMAT 63*6575b268SDan Williams select CXL_PORT 644812be97SDan Williams help 654812be97SDan Williams Enable support for host managed device memory (HDM) resources 664812be97SDan Williams published by a platform's ACPI CXL memory layout description. See 674812be97SDan Williams Chapter 9.14.1 CXL Early Discovery Table (CEDT) in the CXL 2.0 684812be97SDan Williams specification, and CXL Fixed Memory Window Structures (CEDT.CFMWS) 694812be97SDan Williams (https://www.computeexpresslink.org/spec-landing). The CXL core 704812be97SDan Williams consumes these resource to publish the root of a cxl_port decode 714812be97SDan Williams hierarchy to map regions that represent System RAM, or Persistent 724812be97SDan Williams Memory regions to be managed by LIBNVDIMM. 734812be97SDan Williams 744812be97SDan Williams If unsure say 'm'. 758fdcb170SDan Williams 768fdcb170SDan Williamsconfig CXL_PMEM 778fdcb170SDan Williams tristate "CXL PMEM: Persistent Memory Support" 788fdcb170SDan Williams depends on LIBNVDIMM 798fdcb170SDan Williams default CXL_BUS 808fdcb170SDan Williams help 818fdcb170SDan Williams In addition to typical memory resources a platform may also advertise 828fdcb170SDan Williams support for persistent memory attached via CXL. This support is 838fdcb170SDan Williams managed via a bridge driver from CXL to the LIBNVDIMM system 848fdcb170SDan Williams subsystem. Say 'y/m' to enable support for enumerating and 858fdcb170SDan Williams provisioning the persistent memory capacity of CXL memory expanders. 868fdcb170SDan Williams 878fdcb170SDan Williams If unsure say 'm'. 8854cdbf84SBen Widawsky 898dd2bc0fSBen Widawskyconfig CXL_MEM 908dd2bc0fSBen Widawsky tristate "CXL: Memory Expansion" 918dd2bc0fSBen Widawsky depends on CXL_PCI 928dd2bc0fSBen Widawsky default CXL_BUS 938dd2bc0fSBen Widawsky help 948dd2bc0fSBen Widawsky The CXL.mem protocol allows a device to act as a provider of "System 958dd2bc0fSBen Widawsky RAM" and/or "Persistent Memory" that is fully coherent as if the 968dd2bc0fSBen Widawsky memory were attached to the typical CPU memory controller. This is 978dd2bc0fSBen Widawsky known as HDM "Host-managed Device Memory". 988dd2bc0fSBen Widawsky 998dd2bc0fSBen Widawsky Say 'y/m' to enable a driver that will attach to CXL.mem devices for 1008dd2bc0fSBen Widawsky memory expansion and control of HDM. See Chapter 9.13 in the CXL 2.0 1018dd2bc0fSBen Widawsky specification for a detailed description of HDM. 1028dd2bc0fSBen Widawsky 1038dd2bc0fSBen Widawsky If unsure say 'm'. 1048dd2bc0fSBen Widawsky 10554cdbf84SBen Widawskyconfig CXL_PORT 10654cdbf84SBen Widawsky default CXL_BUS 10754cdbf84SBen Widawsky tristate 10854cdbf84SBen Widawsky 1099ea4dcf4SDan Williamsconfig CXL_SUSPEND 1109ea4dcf4SDan Williams def_bool y 1119ea4dcf4SDan Williams depends on SUSPEND && CXL_MEM 1129ea4dcf4SDan Williams 113779dd20cSBen Widawskyconfig CXL_REGION 11445d235c5SDan Williams bool "CXL: Region Support" 115779dd20cSBen Widawsky default CXL_BUS 11623a22cd1SDan Williams # For MAX_PHYSMEM_BITS 11723a22cd1SDan Williams depends on SPARSEMEM 118779dd20cSBen Widawsky select MEMREGION 11923a22cd1SDan Williams select GET_FREE_REGION 12045d235c5SDan Williams help 12145d235c5SDan Williams Enable the CXL core to enumerate and provision CXL regions. A CXL 12245d235c5SDan Williams region is defined by one or more CXL expanders that decode a given 12345d235c5SDan Williams system-physical address range. For CXL regions established by 12445d235c5SDan Williams platform-firmware this option enables memory error handling to 12545d235c5SDan Williams identify the devices participating in a given interleaved memory 12645d235c5SDan Williams range. Otherwise, platform-firmware managed CXL is enabled by being 12745d235c5SDan Williams placed in the system address map and does not need a driver. 12845d235c5SDan Williams 12945d235c5SDan Williams If unsure say 'y' 130779dd20cSBen Widawsky 131d18bc74aSDan Williamsconfig CXL_REGION_INVALIDATION_TEST 132d18bc74aSDan Williams bool "CXL: Region Cache Management Bypass (TEST)" 133d18bc74aSDan Williams depends on CXL_REGION 134d18bc74aSDan Williams help 135d18bc74aSDan Williams CXL Region management and security operations potentially invalidate 136cbbd05d0SRandy Dunlap the content of CPU caches without notifying those caches to 137d18bc74aSDan Williams invalidate the affected cachelines. The CXL Region driver attempts 138d18bc74aSDan Williams to invalidate caches when those events occur. If that invalidation 139d18bc74aSDan Williams fails the region will fail to enable. Reasons for cache 140d18bc74aSDan Williams invalidation failure are due to the CPU not providing a cache 141d18bc74aSDan Williams invalidation mechanism. For example usage of wbinvd is restricted to 142d18bc74aSDan Williams bare metal x86. However, for testing purposes toggling this option 143d18bc74aSDan Williams can disable that data integrity safety and proceed with enabling 144d18bc74aSDan Williams regions when there might be conflicting contents in the CPU cache. 145d18bc74aSDan Williams 146d18bc74aSDan Williams If unsure, or if this kernel is meant for production environments, 147d18bc74aSDan Williams say N. 148d18bc74aSDan Williams 1494cdadfd5SDan Williamsendif 150