Lines Matching +full:hardware +full:- +full:managed

1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4  * Copyright (C) 2008-2009 PetaLogix
17 /* Hardware Page Table Entry */
27 	unsigned long    w:1;	/* Write-thru cache mode */
46 	unsigned long    n:1;	/* No-execute */
55  * tlb_skip size stores actual number skipped TLBs from TLB0 - every directy TLB
62  * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
63  * instruction and data sides share a unified, 64-entry, semi-associative
65  * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
80  * portion. The data portion is 32-bits.
82  * TLB entries are managed entirely under software control by reading,
113 #  define TLB_W			0x00000008 /* Caching is write-through */