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/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO latch controller
10 - Sascha Hauer <s.hauer@pengutronix.de>
13 This binding describes a GPIO multiplexer based on latches connected to
16 CLK0 ----------------------. ,--------.
17 CLK1 -------------------. `--------|> #0 |
19 OUT0 ----------------+--|-----------|D0 Q0|-----|<
[all …]
H A Dsprd,gpio-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
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H A Dfairchild,74hc595.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/fairchild,74hc595.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic 8-bit shift register
11 have a rising-edge triggered latch clock (or storage register clock) pin,
12 which behaves like an active-low chip select.
15 the 74HC595 sees as a rising edge on the latch clock that results in a
21 latch clock * trigger
27 - Maxime Ripard <mripard@kernel.org>
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/linux/drivers/gpio/
H A Dgpio-latch.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO latch driver
7 * This driver implements a GPIO (or better GPO as there is no input)
10 * CLK0 ----------------------. ,--------.
11 * CLK1 -------------------. `--------|> #0 |
13 * OUT0 ----------------+--|-----------|D0 Q0|-----|<
14 * OUT1 --------------+-|--|-----------|D1 Q1|-----|<
15 * OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
16 * OUT3 ----------+-|-|-|--|-----------|D3 Q3|-----|<
17 * OUT4 --------+-|-|-|-|--|-----------|D4 Q4|-----|<
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H A Dgpio-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/gpio/driver.h>
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
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H A Dgpio-pcf857x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders
9 #include <linux/gpio/consumer.h>
10 #include <linux/gpio/driver.h>
61 * that pin be used as an input; it's not an open-drain model, but acts
62 * a bit like one. This is described as "quasi-bidirectional"; read the
65 * Many other I2C GPIO expander chips (like the pca953x models) have
74 unsigned int out; /* software latch */
82 /*-------------------------------------------------------------------------*/
84 /* Talk to 8-bit I/O expander */
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H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/aspeed.h>
11 #include <linux/gpio/driver.h>
26 * These two headers aren't meant to be used by GPIO drivers. We need
31 #include <linux/gpio/consumer.h>
34 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
36 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
76 * represents disabled debouncing for the GPIO. Any other value for an element
98 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
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H A Dgpio-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * gpio-reg: single register individually fixed-direction GPIOs
18 #include <linux/gpio/driver.h>
19 #include <linux/gpio/gpio-reg.h>
37 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN : in gpio_reg_get_direction()
46 if (r->direction & BIT(offset)) in gpio_reg_direction_output()
47 return -ENOTSUPP; in gpio_reg_direction_output()
49 gc->set(gc, offset, value); in gpio_reg_direction_output()
57 return r->direction & BIT(offset) ? 0 : -ENOTSUPP; in gpio_reg_direction_input()
66 spin_lock_irqsave(&r->lock, flags); in gpio_reg_set()
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H A Dgpio-amd8111.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO driver for AMD 8111 south bridges
5 * Copyright (c) 2012 Dmitry Eremin-Solenikov
28 #include <linux/gpio/driver.h>
37 #define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
80 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) & in amd_gpio_request()
83 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_request()
92 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_free()
94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); in amd_gpio_free()
103 spin_lock_irqsave(&agp->lock, flags); in amd_gpio_set()
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/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
8 See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
11 - compatible : shall be one of the following:
12 "marvell,armada-3700-xtal-clock"
13 - #clock-cells : from common clock binding; shall be set to 0
16 - clock-output-names : from common clock binding; allows overwrite default clock
20 pinctrl_nb: pinctrl-nb@13800 {
21 compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
24 xtalclk: xtal-clk {
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/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmaxim,max34408.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Mikhaylov <fr0st61te@gmail.com>
13 The MAX34408/MAX34409 are two- and four-channel current monitors that are
15 unidirectional current sensor offers precision high-side operation with a
16 low full-scale sense voltage. The devices automatically sequence through
17 two or four channels and collect the current-sense samples and average them
19 user-programmable digital thresholds to indicate overcurrent conditions.
24 https://www.analog.com/media/en/technical-documentation/data-sheets/MAX34408-MAX34409.pdf
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/linux/Documentation/devicetree/bindings/mtd/
H A Dfsl-upm-nand.txt4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
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H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
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/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dmicrochip,mcp4821.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 +---------+--------------+-------------+
15 |---------|--------------|-------------|
16 | MCP4801 | 8-bit | 1 |
17 | MCP4802 | 8-bit | 2 |
18 | MCP4811 | 10-bit | 1 |
19 | MCP4812 | 10-bit | 2 |
20 | MCP4821 | 12-bit | 1 |
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/linux/arch/m68k/coldfire/
H A Dm53xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * m53xx.c -- platform support for ColdFire 53xx based boards
7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
56 DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
59 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
60 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
77 CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
94 CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
97 CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
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/linux/arch/m68k/include/asm/
H A Dnettel.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
7 * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
8 * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
9 * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
27 /*---------------------------------------------------------------------------*/
31 * GPIO lines. Most of the LED's are driver through a latch
65 /*---------------------------------------------------------------------------*/
68 * NETtel/5206e based hardware has leds on latch on CS3.
73 /*---------------------------------------------------------------------------*/
[all …]
/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
71 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
72 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
[all …]
/linux/sound/pci/ice1712/
H A Dprodigy_hifi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
63 /* Analog Recording Source :- Mic, LineIn, CD/Video, */
73 /* GPIO pins of envy24ht connected to wm8766 */
75 #define WM8766_SPI_MD (1<<16) /* DATA VT1724 -> WM8766, Pin96 */
76 #define WM8766_SPI_ML (1<<18) /* Latch, Pin98 */
98 #define AK4396_CSN (1 << 8) /* CSN->GPIO
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/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
66 ap-apb@70000000 {
67 compatible = "simple-bus";
[all …]
/linux/drivers/comedi/drivers/
H A Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
143 /* GPIO constants. */
145 * GPIO 0,2,3 = inputs,
180 * Shut down all MC1-controlled
231 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
[all …]
/linux/drivers/net/ethernet/intel/i40e/
H A Di40e_ptp.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
5 #include <linux/posix-clock.h>
39 CANT_DO_PINS = -1,
52 end = -2,
66 led_end = -2,
145 * i40e_ptp_extts0_work - workqueue task function
154 struct i40e_hw *hw = &pf->hw; in i40e_ptp_extts0_work()
169 event.index = hw->pf_id; in i40e_ptp_extts0_work()
172 ptp_clock_event(pf->ptp_clock, &event); in i40e_ptp_extts0_work()
[all …]
/linux/arch/arm/boot/dts/intel/ixp/
H A Dintel-ixp42x-gateworks-gw2348.dts1 // SPDX-License-Identifier: ISC
7 /dts-v1/;
9 #include "intel-ixp42x.dtsi"
10 #include <dt-bindings/input/input.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
25 stdout-path = "uart0:115200n8";
33 compatible = "gpio-leds";
34 led-user {
37 default-state = "on";
[all …]
/linux/Documentation/driver-api/
H A Dmtdnand.rst10 The generic NAND driver supports almost all NAND and AG-AND based chips
31 --------------------------
37 - [MTD Interface]
43 - [NAND Interface]
48 - [GENERIC]
53 - [DEFAULT]
65 -------------------------------
71 - [INTERN]
77 - [REPLACEABLE]
86 - [BOARDSPECIFIC]
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