Home
last modified time | relevance | path

Searched +full:gpio +full:- +full:latch (Results 1 – 25 of 83) sorted by relevance

1234

/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO latch controller
10 - Sascha Hauer <s.hauer@pengutronix.de>
13 This binding describes a GPIO multiplexer based on latches connected to
16 CLK0 ----------------------. ,--------.
17 CLK1 -------------------. `--------|> #0 |
19 OUT0 ----------------+--|-----------|D0 Q0|-----|<
[all …]
H A Dsprd,gpio-eic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/gpio/sprd,gpio-eic.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Orson Zhai <orsonzhai@gmail.com>
12 - Baolin Wang <baolin.wang7@gmail.com>
13 - Chunyan Zhang <zhang.lyra@gmail.com>
19 controller contains 4 sub-modules, i.e. EIC-debounce, EIC-latch, EIC-async and
20 EIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub-
23 The EIC-debounce sub-module provides up to 8 source input signal
[all …]
/linux/drivers/gpio/
H A Dgpio-latch.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO latch driver
7 * This driver implements a GPIO (or better GPO as there is no input)
10 * CLK0 ----------------------. ,--------.
11 * CLK1 -------------------. `--------|> #0 |
13 * OUT0 ----------------+--|-----------|D0 Q0|-----|<
14 * OUT1 --------------+-|--|-----------|D1 Q1|-----|<
15 * OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
16 * OUT3 ----------+-|-|-|--|-----------|D3 Q3|-----|<
17 * OUT4 --------+-|-|-|-|--|-----------|D4 Q4|-----|<
[all …]
H A Dgpio-eic-sprd.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/gpio/driver.h>
54 * The digital-chip EIC controller can support maximum 3 banks, and each bank
60 #define SPRD_EIC_BIT(x) ((x) & (SPRD_EIC_PER_BANK_NR - 1))
67 * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
68 * debounce EIC, latch EIC, async EIC and sync EIC,
71 * (millisecond resolution) and a single-trigger mechanism is introduced
72 * into this sub-module to enhance the input event detection reliability.
75 * The latch EIC is used to latch some special power down signals and
76 * generate interrupts, since the latch EIC does not depend on the APB clock
[all …]
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
50 * represents disabled debouncing for the GPIO. Any other value for an element
72 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
75 uint16_t rdata_reg; /* Rd: read write latch, Wr: <none> */
85 * line even when the GPIO is configured as an output. Since
89 * The "rdata" register returns the content of the write latch
[all …]
H A Dgpio-reg.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * gpio-reg: single register individually fixed-direction GPIOs
18 #include <linux/gpio/driver.h>
19 #include <linux/gpio/gpio-reg.h>
37 return r->direction & BIT(offset) ? GPIO_LINE_DIRECTION_IN : in gpio_reg_get_direction()
46 if (r->direction & BIT(offset)) in gpio_reg_direction_output()
47 return -ENOTSUPP; in gpio_reg_direction_output()
49 gc->set(gc, offset, value); in gpio_reg_direction_output()
57 return r->direction & BIT(offset) ? 0 : -ENOTSUPP; in gpio_reg_direction_input()
66 spin_lock_irqsave(&r->lock, flags); in gpio_reg_set()
[all …]
H A Dgpio-amd8111.c1 // SPDX-License-Identifier: GPL-2.0
3 * GPIO driver for AMD 8111 south bridges
5 * Copyright (c) 2012 Dmitry Eremin-Solenikov
28 #include <linux/gpio/driver.h>
37 #define AMD_GPIO_LTCH_STS 0x40 /* Latch status, w1 */
80 agp->orig[offset] = ioread8(agp->pm + AMD_REG_GPIO(offset)) & in amd_gpio_request()
83 dev_dbg(&agp->pdev->dev, "Requested gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_request()
92 dev_dbg(&agp->pdev->dev, "Freed gpio %d, data %x\n", offset, agp->orig[offset]); in amd_gpio_free()
94 iowrite8(agp->orig[offset], agp->pm + AMD_REG_GPIO(offset)); in amd_gpio_free()
103 spin_lock_irqsave(&agp->lock, flags); in amd_gpio_set()
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 # generic gpio support: platform drivers, dedicated expander chips, etc
4 ccflags-$(CONFIG_DEBUG_GPIO) += -DDEBUG
6 obj-$(CONFIG_GPIOLIB) += gpiolib.o
7 obj-$(CONFIG_GPIOLIB) += gpiolib-devres.o
8 obj-$(CONFIG_GPIOLIB) += gpiolib-legacy.o
9 obj-$(CONFIG_OF_GPIO) += gpiolib-of.o
10 obj-$(CONFIG_GPIO_CDEV) += gpiolib-cdev.o
11 obj-$(CONFIG_GPIO_SYSFS) += gpiolib-sysfs.o
12 obj-$(CONFIG_GPIO_ACPI) += gpiolib-acpi.o
[all …]
/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-xtal-clock.txt4 reading the gpio latch register.
7 of the GPIO block where the gpio latch is located.
8 See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt
11 - compatible : shall be one of the following:
12 "marvell,armada-3700-xtal-clock"
13 - #clock-cells : from common clock binding; shall be set to 0
16 - clock-output-names : from common clock binding; allows overwrite default clock
20 pinctrl_nb: pinctrl-nb@13800 {
21 compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd";
24 xtalclk: xtal-clk {
[all …]
/linux/drivers/staging/fbtft/
H A Dfbtft.h1 /* SPDX-License-Identifier: GPL-2.0+ */
23 * struct fbtft_gpio - Structure that holds one pinname to gpio mapping
25 * @gpio: GPIO number
30 struct gpio_desc *gpio; member
36 * struct fbtft_ops - FBTFT operations structure
47 * @request_gpios_match: Do pinname to gpio matching
76 const struct fbtft_gpio *gpio);
88 * struct fbtft_display - Describes the display properties
124 * struct fbtft_platform_data - Passes display specific data to the driver
126 * @gpios: Pointer to an array of pinname to gpio mappings
[all …]
/linux/Documentation/devicetree/bindings/iio/adc/
H A Dmaxim,max34408.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ivan Mikhaylov <fr0st61te@gmail.com>
13 The MAX34408/MAX34409 are two- and four-channel current monitors that are
15 unidirectional current sensor offers precision high-side operation with a
16 low full-scale sense voltage. The devices automatically sequence through
17 two or four channels and collect the current-sense samples and average them
19 user-programmable digital thresholds to indicate overcurrent conditions.
24 https://www.analog.com/media/en/technical-documentation/data-sheets/MAX34408-MAX34409.pdf
[all …]
/linux/Documentation/devicetree/bindings/mtd/
H A Dfsl-upm-nand.txt4 - compatible : "fsl,upm-nand".
5 - reg : should specify localbus chip select and size used for the chip.
6 - fsl,upm-addr-offset : UPM pattern offset for the address latch.
7 - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
12 - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
[all …]
H A Datmel-nand.txt4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
19 - #address-cells: should be set to 2.
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,armada-37xx-pinctrl.txt1 * Marvell Armada 37xx SoC pin and gpio controller
3 Each Armada 37xx SoC come with two pin and gpio controller one for the
6 Inside this set of register the gpio latch allows exposing some
11 GPIO and pin controller:
12 ------------------------
16 Refer to pinctrl-bindings.txt in this directory for details of the
22 - compatible: "marvell,armada3710-sb-pinctrl", "syscon, "simple-mfd"
24 "marvell,armada3710-nb-pinctrl", "syscon, "simple-mfd"
26 - reg: The first set of register are for pinctrl/gpio and the second
28 - interrupts: list of the interrupt use by the gpio
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmtk-sd.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
16 - enum:
17 - mediatek,mt2701-mmc
18 - mediatek,mt2712-mmc
19 - mediatek,mt6779-mmc
[all …]
/linux/Documentation/devicetree/bindings/iio/dac/
H A Dmicrochip,mcp4821.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 +---------+--------------+-------------+
15 |---------|--------------|-------------|
16 | MCP4801 | 8-bit | 1 |
17 | MCP4802 | 8-bit | 2 |
18 | MCP4811 | 10-bit | 1 |
19 | MCP4812 | 10-bit | 2 |
20 | MCP4821 | 12-bit | 1 |
[all …]
/linux/include/linux/pinctrl/
H A Dpinconf-generic.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
24 * enum pin_config_param - possible pin configuration parameters
25 * @PIN_CONFIG_BIAS_BUS_HOLD: the pin will be set to weakly latch so that it
31 * transition from say pull-up to pull-down implies that you disable
32 * pull-up in the process, this setting disables all biasing.
34 * mode, also know as "third-state" (tristate) or "high-Z" or "floating".
40 * impedance to GROUND). If the argument is != 0 pull-down is enabled,
52 * impedance to VDD). If the argument is != 0 pull-up is enabled,
[all …]
/linux/arch/m68k/coldfire/
H A Dm53xx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * m53xx.c -- platform support for ColdFire 53xx based boards
7 * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
38 DEFINE_CLK(0, "imx1-i2c.0", 22, MCF_CLK);
56 DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
59 DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
60 DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
77 CLKDEV_INIT("imx1-i2c.0", NULL, &__clk_0_22),
94 CLKDEV_INIT("gpio.0", NULL, &__clk_0_41),
97 CLKDEV_INIT("mcfusb-otg.0", NULL, &__clk_0_44),
[all …]
/linux/arch/m68k/include/asm/
H A Dnettel.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * nettel.h -- Lineo (formerly Moreton Bay) NETtel support.
7 * (C) Copyright 1999-2000, Moreton Bay (www.moretonbay.com)
8 * (C) Copyright 2000-2001, Lineo Inc. (www.lineo.com)
9 * (C) Copyright 2001-2002, SnapGear Inc., (www.snapgear.com)
27 /*---------------------------------------------------------------------------*/
31 * GPIO lines. Most of the LED's are driver through a latch
65 /*---------------------------------------------------------------------------*/
68 * NETtel/5206e based hardware has leds on latch on CS3.
73 /*---------------------------------------------------------------------------*/
[all …]
H A Dmcfgpio.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Coldfire generic GPIO support.
11 int __mcfgpio_get_value(unsigned gpio);
12 void __mcfgpio_set_value(unsigned gpio, int value);
13 int __mcfgpio_direction_input(unsigned gpio);
14 int __mcfgpio_direction_output(unsigned gpio, int value);
15 int __mcfgpio_request(unsigned gpio);
16 void __mcfgpio_free(unsigned gpio);
19 #include <linux/gpio.h>
23 static inline int __gpio_get_value(unsigned gpio) in __gpio_get_value() argument
[all …]
/linux/drivers/irqchip/
H A Dirq-aspeed-vic.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7 * Based on irq-vic.c:
9 * Copyright (C) 1999 - 2003 ARM Limited
63 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR); in vic_init_hw()
64 writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4); in vic_init_hw()
67 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR); in vic_init_hw()
68 writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4); in vic_init_hw()
71 writel(0, vic->base + AVIC_INT_SELECT); in vic_init_hw()
72 writel(0, vic->base + AVIC_INT_SELECT + 4); in vic_init_hw()
[all …]
/linux/sound/pci/ice1712/
H A Dprodigy_hifi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
63 /* Analog Recording Source :- Mic, LineIn, CD/Video, */
73 /* GPIO pins of envy24ht connected to wm8766 */
75 #define WM8766_SPI_MD (1<<16) /* DATA VT1724 -> WM8766, Pin96 */
76 #define WM8766_SPI_ML (1<<18) /* Latch, Pin98 */
98 #define AK4396_CSN (1 << 8) /* CSN->GPIO8, pin 75 */
99 #define AK4396_CCLK (1 << 9) /* CCLK->GPIO9, pin 76 */
100 #define AK4396_CDTI (1 << 10) /* CDTI->GPIO10, pin 77 */
116 return ((unsigned short)ice->akm[0].images[reg] << 8) | in wm_get()
117 ice->akm[0].images[reg + 1]; in wm_get()
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-dhcom-som.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2021 DH electronics GmbH
7 #include <dt-bindings/pwm/pwm.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/imx6qdl-clock.h>
10 #include <dt-bindings/input/input.h>
30 memory@10000000 { /* Appropriate memory size will be filled by U-Boot */
35 reg_3p3v: regulator-3P3V {
36 compatible = "regulator-fixed";
37 regulator-always-on;
[all …]
/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
16 compatible = "simple-bus";
17 #address-cells = <2>;
18 #size-cells = <2>;
66 ap-apb@70000000 {
67 compatible = "simple-bus";
[all …]
/linux/drivers/comedi/drivers/
H A Ds626.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * COMEDI - Linux Control and Measurement Device Interface
10 * Copyright (C) 2002-2004 Sensoray Co., Inc.
24 * Number of extended-capability
36 #define S626_RANGE_5V 0x10 /* +/-5V range */
37 #define S626_RANGE_10V 0x00 /* +/-10V range */
143 /* GPIO constants. */
145 * GPIO 0,2,3 = inputs,
180 * Shut down all MC1-controlled
231 #define S626_P_RPS0_TOUT 0x00D4 /* RPS0 time-out. */
[all …]

1234