1 // SPDX-License-Identifier: GPL-2.0-or-later
3  *  Copyright (C) 2015 - Ben Herrenschmidt, IBM Corp.
7  *  Based on irq-vic.c:
9  *  Copyright (C) 1999 - 2003 ARM Limited
63 	writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR);  in vic_init_hw()
64 	writel(0xffffffff, vic->base + AVIC_INT_ENABLE_CLR + 4);  in vic_init_hw()
67 	writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR);  in vic_init_hw()
68 	writel(0xffffffff, vic->base + AVIC_INT_TRIGGER_CLR + 4);  in vic_init_hw()
71 	writel(0, vic->base + AVIC_INT_SELECT);  in vic_init_hw()
72 	writel(0, vic->base + AVIC_INT_SELECT + 4);  in vic_init_hw()
75 	 * (4 GPIO direct inputs), for now we assume this was configured  in vic_init_hw()
78 	sense = readl(vic->base + AVIC_INT_SENSE);  in vic_init_hw()
79 	vic->edge_sources[0] = ~sense;  in vic_init_hw()
80 	sense = readl(vic->base + AVIC_INT_SENSE + 4);  in vic_init_hw()
81 	vic->edge_sources[1] = ~sense;  in vic_init_hw()
84 	writel(0xffffffff, vic->base + AVIC_EDGE_CLR);  in vic_init_hw()
85 	writel(0xffffffff, vic->base + AVIC_EDGE_CLR + 4);  in vic_init_hw()
95 		stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS);  in avic_handle_irq()
97 			stat = readl_relaxed(vic->base + AVIC_IRQ_STATUS + 4);  in avic_handle_irq()
102 		irq += ffs(stat) - 1;  in avic_handle_irq()
103 		generic_handle_domain_irq(vic->dom, irq);  in avic_handle_irq()
110 	unsigned int sidx = d->hwirq >> 5;  in avic_ack_irq()
111 	unsigned int sbit = 1u << (d->hwirq & 0x1f);  in avic_ack_irq()
113 	/* Clear edge latch for edge interrupts, nop for level */  in avic_ack_irq()
114 	if (vic->edge_sources[sidx] & sbit)  in avic_ack_irq()
115 		writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);  in avic_ack_irq()
121 	unsigned int sidx = d->hwirq >> 5;  in avic_mask_irq()
122 	unsigned int sbit = 1u << (d->hwirq & 0x1f);  in avic_mask_irq()
124 	writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);  in avic_mask_irq()
130 	unsigned int sidx = d->hwirq >> 5;  in avic_unmask_irq()
131 	unsigned int sbit = 1u << (d->hwirq & 0x1f);  in avic_unmask_irq()
133 	writel(sbit, vic->base + AVIC_INT_ENABLE + sidx * 4);  in avic_unmask_irq()
140 	unsigned int sidx = d->hwirq >> 5;  in avic_mask_ack_irq()
141 	unsigned int sbit = 1u << (d->hwirq & 0x1f);  in avic_mask_ack_irq()
144 	writel(sbit, vic->base + AVIC_INT_ENABLE_CLR + sidx * 4);  in avic_mask_ack_irq()
146 	/* Then clear edge latch for edge interrupts */  in avic_mask_ack_irq()
147 	if (vic->edge_sources[sidx] & sbit)  in avic_mask_ack_irq()
148 		writel(sbit, vic->base + AVIC_EDGE_CLR + sidx * 4);  in avic_mask_ack_irq()
162 	struct aspeed_vic *vic = d->host_data;  in avic_map()
168 		return -EPERM;  in avic_map()
170 	if (vic->edge_sources[sidx] & sbit)  in avic_map()
190 	if (WARN(parent, "non-root Aspeed VIC not supported"))  in avic_of_init()
191 		return -EINVAL;  in avic_of_init()
193 		return -EINVAL;  in avic_of_init()
197 		return -EIO;  in avic_of_init()
202 		return -ENOMEM;  in avic_of_init()
204 	vic->base = regs;  in avic_of_init()
214 	vic->dom = irq_domain_add_simple(node, NUM_IRQS, 0,  in avic_of_init()
220 IRQCHIP_DECLARE(ast2400_vic, "aspeed,ast2400-vic", avic_of_init);
221 IRQCHIP_DECLARE(ast2500_vic, "aspeed,ast2500-vic", avic_of_init);