18e8e69d6SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2af39bb8bSsfking@fdwdc.com /*
3af39bb8bSsfking@fdwdc.com * Coldfire generic GPIO support.
4af39bb8bSsfking@fdwdc.com *
5af39bb8bSsfking@fdwdc.com * (C) Copyright 2009, Steven King <sfking@fdwdc.com>
6af39bb8bSsfking@fdwdc.com */
7af39bb8bSsfking@fdwdc.com
8af39bb8bSsfking@fdwdc.com #ifndef mcfgpio_h
9af39bb8bSsfking@fdwdc.com #define mcfgpio_h
10af39bb8bSsfking@fdwdc.com
11eac57949SSteven King int __mcfgpio_get_value(unsigned gpio);
12eac57949SSteven King void __mcfgpio_set_value(unsigned gpio, int value);
13eac57949SSteven King int __mcfgpio_direction_input(unsigned gpio);
14eac57949SSteven King int __mcfgpio_direction_output(unsigned gpio, int value);
15eac57949SSteven King int __mcfgpio_request(unsigned gpio);
16eac57949SSteven King void __mcfgpio_free(unsigned gpio);
17af39bb8bSsfking@fdwdc.com
18*863dafa7SGreg Ungerer #ifdef CONFIG_GPIOLIB
19*863dafa7SGreg Ungerer #include <linux/gpio.h>
20*863dafa7SGreg Ungerer #else
21*863dafa7SGreg Ungerer
22eac57949SSteven King /* our alternate 'gpiolib' functions */
__gpio_get_value(unsigned gpio)23eac57949SSteven King static inline int __gpio_get_value(unsigned gpio)
24eac57949SSteven King {
25eac57949SSteven King if (gpio < MCFGPIO_PIN_MAX)
26eac57949SSteven King return __mcfgpio_get_value(gpio);
27eac57949SSteven King else
28eac57949SSteven King return -EINVAL;
29eac57949SSteven King }
30f23c144dSGreg Ungerer
__gpio_set_value(unsigned gpio,int value)31eac57949SSteven King static inline void __gpio_set_value(unsigned gpio, int value)
32eac57949SSteven King {
33eac57949SSteven King if (gpio < MCFGPIO_PIN_MAX)
34eac57949SSteven King __mcfgpio_set_value(gpio, value);
35eac57949SSteven King }
36eac57949SSteven King
__gpio_to_irq(unsigned gpio)37eac57949SSteven King static inline int __gpio_to_irq(unsigned gpio)
38eac57949SSteven King {
39eac57949SSteven King return -EINVAL;
40eac57949SSteven King }
41eac57949SSteven King
gpio_direction_input(unsigned gpio)42eac57949SSteven King static inline int gpio_direction_input(unsigned gpio)
43eac57949SSteven King {
44eac57949SSteven King if (gpio < MCFGPIO_PIN_MAX)
45eac57949SSteven King return __mcfgpio_direction_input(gpio);
46eac57949SSteven King else
47eac57949SSteven King return -EINVAL;
48eac57949SSteven King }
49eac57949SSteven King
gpio_direction_output(unsigned gpio,int value)50eac57949SSteven King static inline int gpio_direction_output(unsigned gpio, int value)
51eac57949SSteven King {
52eac57949SSteven King if (gpio < MCFGPIO_PIN_MAX)
53eac57949SSteven King return __mcfgpio_direction_output(gpio, value);
54eac57949SSteven King else
55eac57949SSteven King return -EINVAL;
56eac57949SSteven King }
57eac57949SSteven King
gpio_request(unsigned gpio,const char * label)58eac57949SSteven King static inline int gpio_request(unsigned gpio, const char *label)
59eac57949SSteven King {
60eac57949SSteven King if (gpio < MCFGPIO_PIN_MAX)
61eac57949SSteven King return __mcfgpio_request(gpio);
62eac57949SSteven King else
63eac57949SSteven King return -EINVAL;
64eac57949SSteven King }
65eac57949SSteven King
gpio_free(unsigned gpio)66eac57949SSteven King static inline void gpio_free(unsigned gpio)
67eac57949SSteven King {
68eac57949SSteven King if (gpio < MCFGPIO_PIN_MAX)
69eac57949SSteven King __mcfgpio_free(gpio);
70eac57949SSteven King }
71eac57949SSteven King
72eac57949SSteven King #endif /* CONFIG_GPIOLIB */
73eac57949SSteven King
74af39bb8bSsfking@fdwdc.com
75c269d4efSGreg Ungerer /*
76eac57949SSteven King * The Freescale Coldfire family is quite varied in how they implement GPIO.
77eac57949SSteven King * Some parts have 8 bit ports, some have 16bit and some have 32bit; some have
78eac57949SSteven King * only one port, others have multiple ports; some have a single data latch
79eac57949SSteven King * for both input and output, others have a separate pin data register to read
80eac57949SSteven King * input; some require a read-modify-write access to change an output, others
81eac57949SSteven King * have set and clear registers for some of the outputs; Some have all the
82eac57949SSteven King * GPIOs in a single control area, others have some GPIOs implemented in
83eac57949SSteven King * different modules.
84c269d4efSGreg Ungerer *
85eac57949SSteven King * This implementation attempts accommodate the differences while presenting
86eac57949SSteven King * a generic interface that will optimize to as few instructions as possible.
87c269d4efSGreg Ungerer */
88eac57949SSteven King #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
89eac57949SSteven King defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
90eac57949SSteven King defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
916eac4027SGreg Ungerer defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
92bea8bcb1SSteven King defined(CONFIG_M5441x)
93c269d4efSGreg Ungerer
94eac57949SSteven King /* These parts have GPIO organized by 8 bit ports */
95eac57949SSteven King
96eac57949SSteven King #define MCFGPIO_PORTTYPE u8
97eac57949SSteven King #define MCFGPIO_PORTSIZE 8
98eac57949SSteven King #define mcfgpio_read(port) __raw_readb(port)
99eac57949SSteven King #define mcfgpio_write(data, port) __raw_writeb(data, port)
100eac57949SSteven King
101eac57949SSteven King #elif defined(CONFIG_M5307) || defined(CONFIG_M5407) || defined(CONFIG_M5272)
102eac57949SSteven King
103eac57949SSteven King /* These parts have GPIO organized by 16 bit ports */
104eac57949SSteven King
105eac57949SSteven King #define MCFGPIO_PORTTYPE u16
106eac57949SSteven King #define MCFGPIO_PORTSIZE 16
107eac57949SSteven King #define mcfgpio_read(port) __raw_readw(port)
108eac57949SSteven King #define mcfgpio_write(data, port) __raw_writew(data, port)
109eac57949SSteven King
11004e037aaSSteven King #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
111eac57949SSteven King
112eac57949SSteven King /* These parts have GPIO organized by 32 bit ports */
113eac57949SSteven King
114eac57949SSteven King #define MCFGPIO_PORTTYPE u32
115eac57949SSteven King #define MCFGPIO_PORTSIZE 32
116eac57949SSteven King #define mcfgpio_read(port) __raw_readl(port)
117eac57949SSteven King #define mcfgpio_write(data, port) __raw_writel(data, port)
118c269d4efSGreg Ungerer
119af39bb8bSsfking@fdwdc.com #endif
120eac57949SSteven King
121eac57949SSteven King #define mcfgpio_bit(gpio) (1 << ((gpio) % MCFGPIO_PORTSIZE))
122eac57949SSteven King #define mcfgpio_port(gpio) ((gpio) / MCFGPIO_PORTSIZE)
123eac57949SSteven King
124eac57949SSteven King #if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
125bea8bcb1SSteven King defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
12683c6bdb8SSteven King defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
12783c6bdb8SSteven King defined(CONFIG_M5441x)
128eac57949SSteven King /*
129eac57949SSteven King * These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
130eac57949SSteven King * read-modify-write to change an output and a GPIO module which has separate
131eac57949SSteven King * set/clr registers to directly change outputs with a single write access.
132eac57949SSteven King */
133eac57949SSteven King #if defined(CONFIG_M528x)
134eac57949SSteven King /*
135eac57949SSteven King * The 528x also has GPIOs in other modules (GPT, QADC) which use
136eac57949SSteven King * read-modify-write as well as those controlled by the EPORT and GPIO modules.
137eac57949SSteven King */
138eac57949SSteven King #define MCFGPIO_SCR_START 40
139bea8bcb1SSteven King #elif defined(CONFIGM5441x)
140bea8bcb1SSteven King /* The m5441x EPORT doesn't have its own GPIO port, uses PORT C */
141bea8bcb1SSteven King #define MCFGPIO_SCR_START 0
142eac57949SSteven King #else
143eac57949SSteven King #define MCFGPIO_SCR_START 8
144eac57949SSteven King #endif
145eac57949SSteven King
146eac57949SSteven King #define MCFGPIO_SETR_PORT(gpio) (MCFGPIO_SETR + \
147eac57949SSteven King mcfgpio_port(gpio - MCFGPIO_SCR_START))
148eac57949SSteven King
149eac57949SSteven King #define MCFGPIO_CLRR_PORT(gpio) (MCFGPIO_CLRR + \
150eac57949SSteven King mcfgpio_port(gpio - MCFGPIO_SCR_START))
151eac57949SSteven King #else
152eac57949SSteven King
153eac57949SSteven King #define MCFGPIO_SCR_START MCFGPIO_PIN_MAX
154eac57949SSteven King /* with MCFGPIO_SCR == MCFGPIO_PIN_MAX, these will be optimized away */
155eac57949SSteven King #define MCFGPIO_SETR_PORT(gpio) 0
156eac57949SSteven King #define MCFGPIO_CLRR_PORT(gpio) 0
157eac57949SSteven King
158eac57949SSteven King #endif
159eac57949SSteven King /*
160eac57949SSteven King * Coldfire specific helper functions
161eac57949SSteven King */
162eac57949SSteven King
163eac57949SSteven King /* return the port pin data register for a gpio */
__mcfgpio_ppdr(unsigned gpio)164eac57949SSteven King static inline u32 __mcfgpio_ppdr(unsigned gpio)
165eac57949SSteven King {
166eac57949SSteven King #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
167eac57949SSteven King defined(CONFIG_M5307) || defined(CONFIG_M5407)
168eac57949SSteven King return MCFSIM_PADAT;
169eac57949SSteven King #elif defined(CONFIG_M5272)
170eac57949SSteven King if (gpio < 16)
171eac57949SSteven King return MCFSIM_PADAT;
172eac57949SSteven King else if (gpio < 32)
173eac57949SSteven King return MCFSIM_PBDAT;
174eac57949SSteven King else
175eac57949SSteven King return MCFSIM_PCDAT;
17604e037aaSSteven King #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
177eac57949SSteven King if (gpio < 32)
178eac57949SSteven King return MCFSIM2_GPIOREAD;
179eac57949SSteven King else
180eac57949SSteven King return MCFSIM2_GPIO1READ;
181eac57949SSteven King #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
182bea8bcb1SSteven King defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
18383c6bdb8SSteven King defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
18483c6bdb8SSteven King defined(CONFIG_M5441x)
185bea8bcb1SSteven King #if !defined(CONFIG_M5441x)
186eac57949SSteven King if (gpio < 8)
187eac57949SSteven King return MCFEPORT_EPPDR;
188eac57949SSteven King #if defined(CONFIG_M528x)
189eac57949SSteven King else if (gpio < 16)
190eac57949SSteven King return MCFGPTA_GPTPORT;
191eac57949SSteven King else if (gpio < 24)
192eac57949SSteven King return MCFGPTB_GPTPORT;
193eac57949SSteven King else if (gpio < 32)
194eac57949SSteven King return MCFQADC_PORTQA;
195eac57949SSteven King else if (gpio < 40)
196eac57949SSteven King return MCFQADC_PORTQB;
197bea8bcb1SSteven King #endif /* defined(CONFIG_M528x) */
198eac57949SSteven King else
199bea8bcb1SSteven King #endif /* !defined(CONFIG_M5441x) */
200eac57949SSteven King return MCFGPIO_PPDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
201eac57949SSteven King #else
202eac57949SSteven King return 0;
203eac57949SSteven King #endif
204eac57949SSteven King }
205eac57949SSteven King
206eac57949SSteven King /* return the port output data register for a gpio */
__mcfgpio_podr(unsigned gpio)207eac57949SSteven King static inline u32 __mcfgpio_podr(unsigned gpio)
208eac57949SSteven King {
209eac57949SSteven King #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
210eac57949SSteven King defined(CONFIG_M5307) || defined(CONFIG_M5407)
211eac57949SSteven King return MCFSIM_PADAT;
212eac57949SSteven King #elif defined(CONFIG_M5272)
213eac57949SSteven King if (gpio < 16)
214eac57949SSteven King return MCFSIM_PADAT;
215eac57949SSteven King else if (gpio < 32)
216eac57949SSteven King return MCFSIM_PBDAT;
217eac57949SSteven King else
218eac57949SSteven King return MCFSIM_PCDAT;
21904e037aaSSteven King #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
220eac57949SSteven King if (gpio < 32)
221eac57949SSteven King return MCFSIM2_GPIOWRITE;
222eac57949SSteven King else
223eac57949SSteven King return MCFSIM2_GPIO1WRITE;
224eac57949SSteven King #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
225bea8bcb1SSteven King defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
22683c6bdb8SSteven King defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
22783c6bdb8SSteven King defined(CONFIG_M5441x)
228bea8bcb1SSteven King #if !defined(CONFIG_M5441x)
229eac57949SSteven King if (gpio < 8)
230eac57949SSteven King return MCFEPORT_EPDR;
231eac57949SSteven King #if defined(CONFIG_M528x)
232eac57949SSteven King else if (gpio < 16)
233eac57949SSteven King return MCFGPTA_GPTPORT;
234eac57949SSteven King else if (gpio < 24)
235eac57949SSteven King return MCFGPTB_GPTPORT;
236eac57949SSteven King else if (gpio < 32)
237eac57949SSteven King return MCFQADC_PORTQA;
238eac57949SSteven King else if (gpio < 40)
239eac57949SSteven King return MCFQADC_PORTQB;
240bea8bcb1SSteven King #endif /* defined(CONFIG_M528x) */
241eac57949SSteven King else
242bea8bcb1SSteven King #endif /* !defined(CONFIG_M5441x) */
243eac57949SSteven King return MCFGPIO_PODR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
244eac57949SSteven King #else
245eac57949SSteven King return 0;
246eac57949SSteven King #endif
247eac57949SSteven King }
248eac57949SSteven King
249eac57949SSteven King /* return the port direction data register for a gpio */
__mcfgpio_pddr(unsigned gpio)250eac57949SSteven King static inline u32 __mcfgpio_pddr(unsigned gpio)
251eac57949SSteven King {
252eac57949SSteven King #if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
253eac57949SSteven King defined(CONFIG_M5307) || defined(CONFIG_M5407)
254eac57949SSteven King return MCFSIM_PADDR;
255eac57949SSteven King #elif defined(CONFIG_M5272)
256eac57949SSteven King if (gpio < 16)
257eac57949SSteven King return MCFSIM_PADDR;
258eac57949SSteven King else if (gpio < 32)
259eac57949SSteven King return MCFSIM_PBDDR;
260eac57949SSteven King else
261eac57949SSteven King return MCFSIM_PCDDR;
26204e037aaSSteven King #elif defined(CONFIG_M5249) || defined(CONFIG_M525x)
263eac57949SSteven King if (gpio < 32)
264eac57949SSteven King return MCFSIM2_GPIOENABLE;
265eac57949SSteven King else
266eac57949SSteven King return MCFSIM2_GPIO1ENABLE;
267eac57949SSteven King #elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
268bea8bcb1SSteven King defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
26983c6bdb8SSteven King defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
27083c6bdb8SSteven King defined(CONFIG_M5441x)
271bea8bcb1SSteven King #if !defined(CONFIG_M5441x)
272eac57949SSteven King if (gpio < 8)
273eac57949SSteven King return MCFEPORT_EPDDR;
274eac57949SSteven King #if defined(CONFIG_M528x)
275eac57949SSteven King else if (gpio < 16)
276eac57949SSteven King return MCFGPTA_GPTDDR;
277eac57949SSteven King else if (gpio < 24)
278eac57949SSteven King return MCFGPTB_GPTDDR;
279eac57949SSteven King else if (gpio < 32)
280eac57949SSteven King return MCFQADC_DDRQA;
281eac57949SSteven King else if (gpio < 40)
282eac57949SSteven King return MCFQADC_DDRQB;
283bea8bcb1SSteven King #endif /* defined(CONFIG_M528x) */
284eac57949SSteven King else
285bea8bcb1SSteven King #endif /* !defined(CONFIG_M5441x) */
286eac57949SSteven King return MCFGPIO_PDDR + mcfgpio_port(gpio - MCFGPIO_SCR_START);
287eac57949SSteven King #else
288eac57949SSteven King return 0;
289eac57949SSteven King #endif
290eac57949SSteven King }
291eac57949SSteven King
292eac57949SSteven King #endif /* mcfgpio_h */
293