| /linux/Documentation/devicetree/bindings/net/ |
| H A D | altr,gmii-to-sgmii-2.0.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 ---
5 $id: http://devicetree.org/schemas/net/altr,gmii-to-sgmii-2.0.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Altera GMII to SGMII Converter
11 - Matthew Gerlach <matthew.gerlach@altera.com>
14 This binding describes the Altera GMII to SGMII converter.
18 const: altr,gmii-to-sgmii-2.0
22 - description: Registers for the emac splitter IP
23 - description: Registers for the GMII to SGMII converter.
[all …]
|
| H A D | altr,socfpga-stmmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthew Gerlach <matthew.gerlach@altera.com>
16 # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
24 - altr,socfpga-stmmac
25 - altr,socfpga-stmmac-a10-s10
26 - altr,socfpga-stmmac-agilex5
29 - compatible
[all …]
|
| H A D | microchip,lan966x-switch.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
[all …]
|
| H A D | xlnx,axi-ethernet.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/xlnx,axi-ethernet.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 provides connectivity to an external ethernet PHY supporting different
12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
22 - Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
27 - xlnx,axi-ethernet-1.00.a
28 - xlnx,axi-ethernet-1.01.a
29 - xlnx,axi-ethernet-2.01.a
[all …]
|
| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
22 LANs. It interfaces directly to twisted pair media via an external
23 transformer. This device interfaces directly to the MAC layer through the
25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
[all …]
|
| H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-phy.yaml#
14 - Andrew Davis <afd@ti.com>
17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver
18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and
19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and
20 100BASE-FX Fiber protocols.
21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
[all …]
|
| H A D | marvell,pp2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marcin Wojtas <mw@semihalf.com>
11 - Russell King <linux@armlinux.org>
15 Marvell Armada 7K/8K Ethernet Controller (PPv2.2)
21 - marvell,armada-375-pp2
22 - marvell,armada-7k-pp22
28 "#address-cells":
31 "#size-cells":
[all …]
|
| H A D | ibm,emac.txt | 4 the Axon bridge. To operate this needs to interact with a this
6 interface. In addition to the nodes and properties described
8 correct clock-frequency property.
13 - device_type : "network"
15 - compatible : compatible list, contains 2 entries, first is
16 "ibm,emac-CHIP" where CHIP is the host ASIC (440gx,
18 "ibm,emac4". For Axon, thus, we have: "ibm,emac-axon",
20 - interrupts : <interrupt mapping for EMAC IRQ and WOL IRQ>
21 - reg : <registers mapping>
22 - local-mac-address : 6 bytes, MAC address
[all …]
|
| H A D | ethernet-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David S. Miller <davem@davemloft.net>
19 max-speed:
24 nvmem-cells:
27 Reference to an nvmem node for the MAC address
29 nvmem-cell-names:
30 const: mac-address
[all …]
|
| H A D | snps,dwmac.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Torgue <alexandre.torgue@foss.st.com>
11 - Giuseppe Cavallaro <peppe.cavallaro@st.com>
12 - Jose Abreu <joabreu@synopsys.com>
15 # will be able to report a warning when we have that compatible, since
16 # we will validate the node thanks to the select, but won't report it
23 - snps,dwmac
24 - snps,dwmac-3.40a
[all …]
|
| /linux/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac1000.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
38 #define GMAC_INT_DISABLE_PCSAN BIT(2)
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
77 /* SGMII/RGMII status register */
79 #define GMAC_RGSMIIIS_SPEED GENMASK(2, 1)
93 #define GMAC_CONTROL_2K 0x08000000 /* IEEE 802.3as 2K packets */
94 #define GMAC_CONTROL_TC 0x01000000 /* Transmit Conf. in RGMII/SGMII */
[all …]
|
| H A D | dwmac-socfpga.c | 1 // SPDX-License-Identifier: GPL-2.0-only
4 * Adopted from dwmac-sti.c
7 #include <linux/mfd/altera-sysmgr.h>
13 #include <linux/mdio/mdio-regmap.h>
14 #include <linux/pcs-lynx.h>
24 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
68 struct stmmac_priv *priv = netdev_priv(dev_get_drvdata(dwmac->dev)); in socfpga_dwmac_fix_mac_speed()
69 void __iomem *splitter_base = dwmac->splitter_base; in socfpga_dwmac_fix_mac_speed()
70 void __iomem *sgmii_adapter_base = dwmac->sgmii_adapter_base; in socfpga_dwmac_fix_mac_speed()
97 if ((priv->plat->phy_interface == PHY_INTERFACE_MODE_SGMII || in socfpga_dwmac_fix_mac_speed()
[all …]
|
| /linux/arch/mips/cavium-octeon/executive/ |
| H A D | cvmx-helper-board.c | 7 * Copyright (c) 2003-2008 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
30 * Helper functions to abstract board specific data about
31 * network ports from the rest of the cvmx-helper files.
36 #include <asm/octeon/cvmx-bootinfo.h>
38 #include <asm/octeon/cvmx-config.h>
40 #include <asm/octeon/cvmx-helper.h>
[all …]
|
| H A D | cvmx-interrupt-rsl.c | 7 * Copyright (c) 2003-2008 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
29 * Utility functions to decode Octeon's RSL_INT_BLOCKS
35 #include <asm/octeon/cvmx-asxx-defs.h>
36 #include <asm/octeon/cvmx-gmxx-defs.h>
48 * @block: Interface to enable 0-1
74 * @interface: Interface to enable
[all …]
|
| H A D | cvmx-helper.c | 7 * Copyright (c) 2003-2008 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
36 #include <asm/octeon/cvmx-config.h>
38 #include <asm/octeon/cvmx-fpa.h>
39 #include <asm/octeon/cvmx-pip.h>
40 #include <asm/octeon/cvmx-pko.h>
41 #include <asm/octeon/cvmx-ipd.h>
[all …]
|
| H A D | cvmx-helper-util.c | 7 * Copyright (c) 2003-2008 Cavium Networks
10 * it under the terms of the GNU General Public License, Version 2, as
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
35 #include <asm/octeon/cvmx-config.h>
37 #include <asm/octeon/cvmx-fpa.h>
38 #include <asm/octeon/cvmx-pip.h>
39 #include <asm/octeon/cvmx-pko.h>
40 #include <asm/octeon/cvmx-ipd.h>
[all …]
|
| /linux/drivers/net/ethernet/freescale/dpaa2/ |
| H A D | dpmac.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2013-2016 Freescale Semiconductor Inc.
24 * enum dpmac_link_type - DPMAC link type
38 * enum dpmac_eth_if - DPMAC Ethrnet interface
42 * @DPMAC_ETH_IF_GMII: GMII interface
44 * @DPMAC_ETH_IF_SGMII: SGMII interface
68 * struct dpmac_attr - Structure representing DPMAC attributes
70 * @max_rate: Maximum supported rate - in Mbps
90 #define DPMAC_LINK_OPT_PAUSE BIT_ULL(2)
96 #define DPMAC_ADVERTISED_1000BASET_FULL BIT_ULL(2)
[all …]
|
| /linux/drivers/net/phy/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
19 Ethernet controllers are usually attached to PHY
35 Adds support for a set of LED trigger events per-PHY. Link
39 logical-or of all the link speed ones.
40 All these triggers are named according to the following pattern:
45 for any speed known to the PHY.
61 Adds the platform "fixed" MDIO Bus to cover the boards that use
62 PHYs that are not connected to the real MDIO bus.
64 Currently tested with mpc866ads and mpc8349e-mitx.
116 - ADIN1200 - Robust,Industrial, Low Power 10/100 Ethernet PHY
[all …]
|
| /linux/drivers/net/ethernet/xilinx/ |
| H A D | xilinx_axienet.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright (c) 2010 - 2012 Xilinx, Inc. All rights reserved.
39 #define XAE_OPTION_VLAN BIT(2)
58 * allow these types of frames to be received. Default: enabled (set)
121 /* Constant to convert delay counts to microseconds */
148 #define XAE_IFGP_OFFSET 0x00000008 /* Tx Inter-frame gap adjustment*/
178 #define XAE_AM0_OFFSET 0x00000750 /* Frame Filter Mask Value Bytes 3-0 */
179 #define XAE_AM1_OFFSET 0x00000754 /* Frame Filter Mask Value Bytes 7-4 */
206 /* Transmit inter-frame gap adjustment value */
240 /* In-Band FCS enable (FCS not stripped) */
[all …]
|
| /linux/Documentation/networking/ |
| H A D | phy.rst | 9 to a MAC layer, which communicates with the physical connection through a
12 cable), and provides a register interface to allow drivers to determine what
13 settings were chosen, and to configure what settings are allowed.
15 While these devices are distinct from the network devices, and conform to a
16 standard layout for the registers, it has been common practice to integrate
19 sometimes quite different) ethernet controllers connected to the same
20 management bus, it is difficult to ensure safe use of the bus.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
[all …]
|
| /linux/Documentation/devicetree/bindings/net/dsa/ |
| H A D | mediatek,mt7530.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Arınç ÜNAL <arinc.unal@arinc9.com>
11 - Landen Chao <Landen.Chao@mediatek.com>
12 - DENG Qingfang <dqfext@gmail.com>
13 - Sean Wang <sean.wang@mediatek.com>
14 - Daniel Golle <daniel@makrotopia.org>
17 There are three versions of MT7530, standalone, in a multi-chip module and
18 built-into a SoC.
[all …]
|
| /linux/Documentation/networking/device_drivers/ethernet/stmicro/ |
| H A D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
[all …]
|
| /linux/include/linux/ |
| H A D | phy.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Based on code in sungem_phy.c and (long-removed) gianfar_phy.c
56 * Set phydev->irq to PHY_POLL if interrupts are not supported,
57 * or not desired for this PHY. Set to PHY_MAC_INTERRUPT if
60 #define PHY_POLL -1
61 #define PHY_MAC_INTERRUPT -2
70 * enum phy_interface_t - Interface Mode definitions
72 * @PHY_INTERFACE_MODE_NA: Not Applicable - don't touch
74 * @PHY_INTERFACE_MODE_MII: Media-independent interface
75 * @PHY_INTERFACE_MODE_GMII: Gigabit media-independent interface
[all …]
|
| /linux/drivers/net/ethernet/freescale/fman/ |
| H A D | fman_memac.c | 1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later
3 * Copyright 2008 - 2015 Freescale Semiconductor Inc.
14 #include <linux/pcs-lynx.h>
56 #define IF_MODE_MASK 0x00000003 /* 30-31 Mask on i/f mode bits */
57 #define IF_MODE_10G 0x00000000 /* 30-31 10G interface */
58 #define IF_MODE_MII 0x00000001 /* 30-31 MII interface */
59 #define IF_MODE_GMII 0x00000002 /* 30-31 GMII (1G) interface */
62 #define IF_MODE_RGMII_1000 0x00004000 /* 10 - 1000Mbps RGMII */
63 #define IF_MODE_RGMII_100 0x00000000 /* 00 - 100Mbps RGMII */
64 #define IF_MODE_RGMII_10 0x00002000 /* 01 - 10Mbps RGMII */
[all …]
|
| /linux/drivers/net/ethernet/microchip/ |
| H A D | lan743x_main.c | 1 /* SPDX-License-Identifier: GPL-2.0+ */
24 #define MMD_ACCESS_READ 2
42 netif_err(adapter, drv, adapter->netdev, in pci11x1x_strap_get_status()
55 adapter->is_sgmii_en = true; in pci11x1x_strap_get_status()
57 adapter->is_sgmii_en = false; in pci11x1x_strap_get_status()
62 adapter->is_sgmii_en = true; in pci11x1x_strap_get_status()
64 adapter->is_sgmii_en = false; in pci11x1x_strap_get_status()
66 adapter->is_sgmii_en = false; in pci11x1x_strap_get_status()
69 netif_dbg(adapter, drv, adapter->netdev, in pci11x1x_strap_get_status()
70 "SGMII I/F %sable\n", adapter->is_sgmii_en ? "En" : "Dis"); in pci11x1x_strap_get_status()
[all …]
|