xref: /linux/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml (revision 8be4d31cb8aaeea27bde4b7ddb26e28a89062ebf) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Altera SOCFPGA SoC DWMAC controller
8
9maintainers:
10  - Matthew Gerlach <matthew.gerlach@altera.com>
11
12description:
13  This binding describes the Altera SOCFPGA SoC implementation of the
14  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
15  families of chips.
16  # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
17  # does not validate against net/snps,dwmac.yaml.
18
19select:
20  properties:
21    compatible:
22      contains:
23        enum:
24          - altr,socfpga-stmmac
25          - altr,socfpga-stmmac-a10-s10
26          - altr,socfpga-stmmac-agilex5
27
28  required:
29    - compatible
30
31properties:
32  compatible:
33    oneOf:
34      - items:
35          - const: altr,socfpga-stmmac
36          - const: snps,dwmac-3.70a
37          - const: snps,dwmac
38      - items:
39          - const: altr,socfpga-stmmac-a10-s10
40          - const: snps,dwmac-3.72a
41          - const: snps,dwmac
42      - items:
43          - const: altr,socfpga-stmmac-a10-s10
44          - const: snps,dwmac-3.74a
45          - const: snps,dwmac
46      - items:
47          - const: altr,socfpga-stmmac-agilex5
48          - const: snps,dwxgmac-2.10
49
50  clocks:
51    minItems: 1
52    items:
53      - description: GMAC main clock
54      - description:
55          PTP reference clock. This clock is used for programming the
56          Timestamp Addend Register. If not passed then the system
57          clock will be used and this is fine on some platforms.
58
59  clock-names:
60    minItems: 1
61    items:
62      - const: stmmaceth
63      - const: ptp_ref
64
65  iommus:
66    minItems: 1
67    maxItems: 2
68
69  phy-mode:
70    enum:
71      - gmii
72      - mii
73      - rgmii
74      - rgmii-id
75      - rgmii-rxid
76      - rgmii-txid
77      - sgmii
78      - 1000base-x
79
80  rxc-skew-ps:
81    description: Skew control of RXC pad
82
83  rxd0-skew-ps:
84    description: Skew control of RX data 0 pad
85
86  rxd1-skew-ps:
87    description: Skew control of RX data 1 pad
88
89  rxd2-skew-ps:
90    description: Skew control of RX data 2 pad
91
92  rxd3-skew-ps:
93    description: Skew control of RX data 3 pad
94
95  rxdv-skew-ps:
96    description: Skew control of RX CTL pad
97
98  txc-skew-ps:
99    description: Skew control of TXC pad
100
101  txen-skew-ps:
102    description: Skew control of TXC pad
103
104  altr,emac-splitter:
105    $ref: /schemas/types.yaml#/definitions/phandle
106    description:
107      Should be the phandle to the emac splitter soft IP node if DWMAC
108      controller is connected an emac splitter.
109
110  altr,f2h_ptp_ref_clk:
111    $ref: /schemas/types.yaml#/definitions/phandle
112    description:
113      Phandle to Precision Time Protocol reference clock. This clock is
114      common to gmac instances and defaults to osc1.
115
116  altr,gmii-to-sgmii-converter:
117    $ref: /schemas/types.yaml#/definitions/phandle
118    description:
119      Should be the phandle to the gmii to sgmii converter soft IP.
120
121  altr,sysmgr-syscon:
122    $ref: /schemas/types.yaml#/definitions/phandle-array
123    description:
124      Should be the phandle to the system manager node that encompass
125      the glue register, the register offset, and the register shift.
126      On Cyclone5/Arria5, the register shift represents the PHY mode
127      bits, while on the Arria10/Stratix10/Agilex platforms, the
128      register shift represents bit for each emac to enable/disable
129      signals from the FPGA fabric to the EMAC modules.
130    items:
131      - items:
132          - description: phandle to the system manager node
133          - description: offset of the control register
134          - description: shift within the control register
135
136patternProperties:
137  "^mdio[0-9]$":
138    type: object
139
140required:
141  - compatible
142  - clocks
143  - clock-names
144  - altr,sysmgr-syscon
145
146allOf:
147  - $ref: snps,dwmac.yaml#
148
149unevaluatedProperties: false
150
151examples:
152
153  - |
154    #include <dt-bindings/interrupt-controller/arm-gic.h>
155    #include <dt-bindings/interrupt-controller/irq.h>
156    soc {
157        #address-cells = <1>;
158        #size-cells = <1>;
159        ethernet@ff700000 {
160            compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a",
161            "snps,dwmac";
162            altr,sysmgr-syscon = <&sysmgr 0x60 0>;
163            reg = <0xff700000 0x2000>;
164            interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
165            interrupt-names = "macirq";
166            mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
167            clocks = <&emac_0_clk>;
168            clock-names = "stmmaceth";
169            phy-mode = "sgmii";
170        };
171    };
172