Lines Matching +full:gmii +full:- +full:to +full:- +full:sgmii +full:- +full:2
9 to a MAC layer, which communicates with the physical connection through a
12 cable), and provides a register interface to allow drivers to determine what
13 settings were chosen, and to configure what settings are allowed.
15 While these devices are distinct from the network devices, and conform to a
16 standard layout for the registers, it has been common practice to integrate
19 sometimes quite different) ethernet controllers connected to the same
20 management bus, it is difficult to ensure safe use of the bus.
26 #. Increase code-reuse
27 #. Increase overall code-maintainability
30 Basically, this layer is meant to provide an interface to PHY devices which
31 allows network driver writers to write as little code as possible, while
37 Most network devices are connected to a PHY by means of a management bus.
39 In order to take advantage of the PAL, each bus interface needs to be
48 number. These functions are guaranteed not to be called from interrupt
49 time, so it is safe for them to block, waiting for an interrupt to signal
52 #. A reset function is optional. This is used to return the bus to an
57 mdiobus_register. Similarly, there's a remove function to undo all of
61 exit functions are used to register the driver.
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
74 data lines. Due to this design decision, a 1.5ns to 2ns delay must be added
75 between the clock line (RXC or TXC) and the data lines to let the PHY (clock
76 sink) have a large enough setup and hold time to sample the data lines correctly. The
77 PHY library offers different types of PHY_INTERFACE_MODE_RGMII* values to let
80 device itself, leading to the following:
84 or the PCB traces insert the correct 1.5-2ns delay
93 both transmit AND receive data lines from/to the PHY device
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
98 receiver/transmitter side delay (e.g: 0.5, 1.0, 1.5ns) to be specified. Such
99 precision may be required to account for differences in PCB trace lengths
105 * PHY device drivers in PHYLIB being reusable by nature, being able to
107 requirements to be operated correctly
112 configured correctly in order to provide the required transmit and/or receive
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
124 option to insert the expected 2ns RGMII delay.
126 * Modifying the PCB design to include a fixed delay (e.g: using a specifically
130 -----------------------------------------
133 will most likely result in the clock and data line signals to be unstable when
134 the PHY or MAC take a snapshot of these signals to translate them into logical
144 * Switching to lower speeds such as 10/100Mbits/sec makes the problem go away
147 Connecting to a PHY
150 Sometime during startup, the network driver needs to establish a connection
152 and drivers need to all have been loaded, so it is ready for the connection.
153 At this point, there are several ways to connect to the PHY:
162 allowing the network driver to react first to any changes before the PAL
166 manually calling functions to update status, and configure the PHY
172 If you choose option 1 (The hope is that every driver can, but to still be
173 useful to drivers that can't), connecting to the PHY is simple:
175 First, you need a function to react to changes in the link state. This
180 Next, you need to know the device name of the PHY connected to this device.
185 Now, to connect, just call this function::
189 *phydev* is a pointer to the phy_device structure which represents the PHY.
191 pointer to your net_device. Once done, this function will have started the
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
198 to phy_connect() such that the underlying PHY driver can check for flags
201 the PHY/controller, of which the PHY needs to be aware.
204 between the controller and the PHY. Examples are GMII, MII,
205 RGMII, and SGMII. See "PHY interface mode" below. For a full
208 Now just make sure that phydev->supported and phydev->advertising have any
210 controller may be connected to a gigabit capable PHY, so you would need to
216 Lastly, once the controller is ready to handle network traffic, you call
218 PHY to connect to the network. If the MAC interrupt of your network driver
219 also handles PHY status changes, just set phydev->irq to PHY_MAC_INTERRUPT
221 driver. If you don't want to use interrupts, set phydev->irq to PHY_POLL.
225 When you want to disconnect from the network (even if just briefly), you call
234 guaranteed to remain constant; there are PHYs which dynamically change
246 This defines the 1000BASE-X single-lane serdes link as defined by the
249 data rate of 1Gbps. Embedded in the data stream is a 16-bit control
250 word which is used to negotiate the duplex and pause modes with the
251 remote end. This does not include "up-clocked" variants such as 2.5Gbps
255 This defines a variant of 1000BASE-X which is clocked 2.5 times as fast
259 This is used for Cisco SGMII, which is a modification of 1000BASE-X
260 as defined by the 802.3 standard. The SGMII link consists of a single
264 The 802.3 control word is re-purposed to send the negotiated speed and
265 duplex information from to the MAC, and for the MAC to acknowledge
266 receipt. This does not include "up-clocked" variants such as 2.5Gbps
269 Note: mismatched SGMII vs 1000BASE-X configuration on a link can
270 successfully pass data in some circumstances, but the 16-bit control
276 This is the IEEE 802.3 Clause 129 defined 5GBASE-R protocol. It is
277 identical to the 10GBASE-R protocol defined in Clause 49, with the
278 exception that it operates at half the frequency. Please refer to the
282 This is the IEEE 802.3 Clause 49 defined 10GBASE-R protocol used with
283 various different mediums. Please refer to the IEEE standard for a
286 Note: 10GBASE-R is just one protocol that can be used with XFI and SFI.
293 This is the IEEE 802.3 Clause 49 defined 10GBASE-R with Clause 73
294 autonegotiation. Please refer to the IEEE standard for further
297 Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
301 This is the IEEE 802.3 PCS Clause 107 defined 25GBASE-R protocol.
302 The PCS is identical to 10GBASE-R, i.e. 64B/66B encoded
304 Please refer to the IEEE standard for further information.
313 the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses
314 a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not
315 only the port id, but also so-called "extensions". The only documented
316 extension so-far in the specification is the inclusion of timestamps, for
317 PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
321 This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
322 autonegotiation. Generally, it will be used with a Clause 70 PMD. To
323 contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
327 This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
328 SGMII lines into a single link compared to 4 on QSGMII.
331 Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
337 Non-standard, simplified MII mode, without TXER, RXER, CRS and COL signals
338 as defined for the MII. The absence of COL signal makes half-duplex link
339 modes impossible but does not interfere with BroadR-Reach link modes on
340 Broadcom (and other two-wire Ethernet) PHYs, because they are full-duplex
348 MII_ADVERTISE to indicate towards the link partner that the Ethernet MAC
360 It is possible that the PAL's built-in state machine needs a little help to
362 register a helper function when connecting to the PHY, which will be called
363 every second before the state machine reacts to any changes. To do this, you
364 need to manually call phy_attach() and phy_prepare_link(), and then call
365 phy_start_machine() with the second argument set to point to your special
368 Currently there are no examples of how to use this functionality, and testing
375 There's a remote chance that the PAL's built-in state machine cannot track
378 phy_prepare_link(). This will mean that phydev->state is entirely yours to
380 might need to avoid them).
382 An effort has been made to make sure that useful functionality can be
383 accessed without the state-machine running, and most of these functions are
384 descended from functions which did not interact with a complex state-machine.
385 However, again, no effort has been made so far to test running without the
399 A convenience function to print out the PHY status neatly.
410 Attaches a network device to a particular PHY, binding the PHY to a generic
423 Fills the phydev structure with up-to-date information about the current
437 machine if you write registers like BMCR, BMSR, ADVERTISE, etc. Best to
438 use this only to write registers which are not standard, and don't set off
446 many PHYs require a little hand-holding to get up-and-running.
449 ------------------
452 features you want to support, then it may be best to not add
457 --------------------
459 If you do need to write a PHY driver, the first thing to do is
462 UID (stored in registers 2 and 3), then comparing it to each
473 Next, you need to specify what features (speed, duplex, autoneg,
481 Of these, only config_aneg and read_status are required to be
483 preferred to use the generic phy driver's versions of these two
486 you only need to perform some actions before and after invoking
490 Feel free to look at the Marvell, Cicada, and Davicom drivers in
498 standardized by the IEEE. Most modern PHYs will be able to use
501 implemented in the PAL. This support uses the PAL to access MMD
512 special handling. For instance, to change where the PHY's clock input is,
513 or to add a delay to account for latency issues in the data path. In order
514 to support such contingencies, the PHY Layer allows platform code to register
515 fixups to be run when the PHY is brought up (or subsequently reset).
517 When the PHY Layer brings up a PHY it checks to see if there are any fixups
519 field) and the bus identifier (contained in phydev->dev.bus_id). Both must
524 with the fixup. This function is passed a pointer to the phy_device of
541 The stubs set one of the two matching criteria, and set the other one to
545 time, the module needs to unregister the fixup and free allocated memory when
558 http://standards.ieee.org/getieee802/download/802.3-2008_section2.pdf