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/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
18 supply, vsync input from IR camera, and fsin1/fsin2 output fo
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/freebsd/usr.bin/clang/llc/
H A Dllc.14 .nr rst2man-indent-level 0
7 \\$1 \\n[an-margin]
8 level \\n[rst2man-indent-level]
9 level margin: \\n[rst2man-indent\\n[rst2man-indent-level]]
10 -
11 \\n[rst2man-indent0]
12 \\n[rst2man-indent1]
13 \\n[rst2man-indent2]
18 . nr rst2man-indent\\n[rst2man-indent-level] \\n[an-margin]
19 . nr rst2man-indent-level +1
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h1 //===-- llvm/CodeGen/ISDOpcodes.h - CodeGen opcodes -------------*- C++ -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
20 /// ISD namespace - This namespace contains an enum which represents all of the
25 //===--------------------------------------------------------------------===//
26 /// ISD::NodeType enum - This enum defines the target-independent operators
29 /// Targets may also define target-dependent operator codes for SDNodes. For
31 /// Targets should aim to use target-independent operators to model their
32 /// instruction sets as much as possible, and only use target-dependent
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/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td1 //===- TargetSelectionDAG.td - Common code for DAG isels ---*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // This file defines the target-independent interfaces used by SelectionDAG
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
25 // SDTCisVT - The specified operand has exactly this VT.
32 // SDTCisInt - The specified operand has integer type.
35 // SDTCisFP - The specified operand has floating-point type.
38 // SDTCisVec - The specified operand has a vector type.
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFPStack.td1 //===- X86InstrFPStack.td - FPU Instruction Set --------
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1 //===-- R600ISelLowering.cpp - R600 DAG Lowering Implementation -----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
43 computeRegisterProperties(Subtarget->getRegisterInfo()); in R600TargetLowering()
95 setOperationAction({ISD::FCOS, ISD::FSIN}, MVT::f32, Custom); in R600TargetLowering()
118 if (Subtarget->hasCARRY()) in R600TargetLowering()
121 if (Subtarget->hasBORROW()) in R600TargetLowering()
125 if (!Subtarget->hasBFE()) in R600TargetLowering()
130 if (!Subtarget->hasBFE()) in R600TargetLowering()
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H A DSIISelLowering.cpp1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
49 #define DEBUG_TYPE "si-lower"
54 "amdgpu-disable-loop-alignment",
59 "amdgpu-use-divergent-register-indexing",
66 return Info->getMode().FP32Denormals == DenormalMode::getPreserveSign(); in denormalModeIsFlushAllF32()
71 return Info->getMode().FP64FP16Denormals == DenormalMode::getPreserveSign(); in denormalModeIsFlushAllF64F16()
97 const TargetRegisterClass *V64RegClass = TRI->getVGPR64Class(); in SITargetLowering()
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H A DAMDGPUISelLowering.cpp1 //===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
35 "amdgpu-bypass-slow-div",
36 cl::desc("Skip 64-bit divide for dynamic 32-bit values"),
56 // In order for this to be a signed 24-bit value, bit 23, must in numBitsSigned()
181 // There are no 64-bit extloads. These should be done as a 32-bit extload and in AMDGPUTargetLowering()
182 // an extension to 64-bit. in AMDGPUTargetLowering()
411 if (Subtarget->has16BitInsts()) in AMDGPUTargetLowering()
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H A DAMDGPUISelDAGToDAG.cpp1 //===-- AMDGPUISelDAGToDAG.cpp - A dag to dag inst selector for AMDGPU ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //==-----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "amdgpu-isel"
43 //===----------------------------------------------------------------------===//
45 //===----------------------------------------------------------------------===//
52 // Figure out if this is really an extract of the high 16-bits of a dword.
58 if (!Idx->isOne()) in isExtractHiElt()
71 if (ShiftAmt->getZExtValue() == 16) { in isExtractHiElt()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeFloatTypes.cpp1 //===-------- LegalizeFloatTypes.cpp - Legalization of float types --------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
19 //===----------------------------------------------------------------------===//
27 #define DEBUG_TYPE "legalize-types"
29 /// GetFPLibCall - Return the right libcall for the given floating point type.
47 //===----------------------------------------------------------------------===//
49 //===----------------------------------------------------------------------===//
52 LLVM_DEBUG(dbgs() << "Soften float result " << ResNo << ": "; N->dump(&DAG)); in SoftenFloatResult()
55 switch (N->getOpcode()) { in SoftenFloatResult()
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H A DLegalizeDAG.cpp1 //===- LegalizeDAG.cpp - Implement SelectionDAG::Legalize -----------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
62 /// Keeps track of state when getting the sign of a floating-point value as an
76 //===----------------------------------------------------------------------===//
126 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
210 UpdatedNodes->insert(N); in ReplacedNode()
214 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
215 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
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H A DLegalizeVectorTypes.cpp1 //===------- LegalizeVectorTypes.cpp - Legalization of vector types -------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // Scalarization is the act of changing a computation in an illegal one-element
20 //===----------------------------------------------------------------------===//
35 #define DEBUG_TYPE "legalize-types"
37 //===----------------------------------------------------------------------===//
38 // Result Vector Scalarization: <1 x ty> -> ty.
39 //===----------------------------------------------------------------------===//
43 N->dump(&DAG)); in ScalarizeVectorResult()
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H A DSelectionDAGBuilder.cpp1 //===- SelectionDAGBuilder.cpp - Selection-DAG building -------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
119 /// LimitFloatPrecision - Generate low-precision inline sequences for
124 InsertAssertAlign("insert-assert-align", cl::init(true),
129 LimitFPPrecision("limit-float-precision",
130 cl::desc("Generate low-precision inline sequences "
136 "switch-peel-threshold", cl::Hidden, cl::init(66),
142 // DAG-based analysis from blowing up. For example, alias analysis and
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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp1 //===-- CSKYISelLowering.cpp - CSKY DAG Lowering Implementation ----------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
28 #define DEBUG_TYPE "csky-isel-lowering"
120 ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, in CSKYTargetLowering()
380 // large enough to hold a0-a4. in LowerFormalArguments()
389 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
390 VaArgOffset = -VarArgsSaveSize; in LowerFormalArguments()
396 CSKYFI->setVarArgsFrameIndex(FI); in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
106 // Allocate a full-sized argument for the 64-bit ABI.
112 "Can't handle non-64 bits locations"); in Analyze_CC_Sparc64_Full()
121 // Promote integers to %i0-%i5. in Analyze_CC_Sparc64_Full()
124 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). in Analyze_CC_Sparc64_Full()
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/freebsd/contrib/one-true-awk/
H A Drun.c51 if (p->ctype == OCELL && (p->csub < CUNK || p->csub > CFREE)) { in tempfree()
53 p->csub, p->ctype, p->sval); in tempfree()
118 int boff = pbptr ? *pbptr - *pbuf : 0; in adjbuf()
121 minlen += quantum - rminlen; in adjbuf()
153 for (a = u; ; a = a->nnext) { in execute()
156 x = (Cell *) (a->narg[0]); in execute()
163 if (notlegal(a->nobj)) /* probably a Cell* but too risky to print */ in execute()
165 proc = proctab[a->nobj-FIRSTTOKEN]; in execute()
166 x = (*proc)(a->narg, a->nobj); in execute()
175 if (a->nnext == NULL) in execute()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1 //===-- HexagonISelLowering.cpp - Hexagon DAG Lowering Implementation -----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
69 #define DEBUG_TYPE "hexagon-lowering"
71 static cl::opt<bool> EmitJumpTables("hexagon-emit-jump-tables",
76 EnableHexSDNodeSched("enable-hexagon-sdnode-sched", cl::Hidden,
79 static cl::opt<bool> EnableFastMath("ffast-math", cl::Hidden,
82 static cl::opt<int> MinimumJumpTables("minimum-jump-tables", cl::Hidden,
87 MaxStoresPerMemcpyCL("max-store-memcpy", cl::Hidden, cl::init(6),
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
106 #define DEBUG_TYPE "ppc-lowering"
108 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
111 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
114 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
117 static cl::opt<bool> DisableSCO("disable-ppc-sco",
120 static cl::opt<bool> DisableInnermostLoopAlign32("disable-ppc-innermost-loop-align32",
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1 //===- MipsISelLowering.cpp - Mips DAG Lowering Implementation ------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
82 #define DEBUG_TYPE "mips-lower"
87 NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
142 return DAG.getRegister(FI->getGlobalBaseReg(MF), Ty); in getGlobalReg()
148 return DAG.getTargetGlobalAddress(N->getGlobal(), SDLoc(N), Ty, 0, Flag); in getTargetNode()
154 return DAG.getTargetExternalSymbol(N->getSymbol(), Ty, Flag); in getTargetNode()
160 return DAG.getTargetBlockAddress(N->getBlockAddress(), Ty, 0, Flag); in getTargetNode()
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H A DMipsSEISelLowering.cpp1 //===- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface -------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
52 #define DEBUG_TYPE "mips-isel"
55 UseMipsTailCalls("mips-tail-calls", cl::Hidden,
58 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
122 // f16 is a storage-only type, always promote it to f32. in MipsSETargetLowering()
145 setOperationAction(ISD::FSIN, MVT::f16, Promote); in MipsSETargetLowering()
225 // MIPS32r6 replaces the accumulator-based multiplies with a three register in MipsSETargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "ve-lower"
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
91 if (Subtarget->enableVPU()) { in initRegisterClasses()
212 // VE doesn't have instructions for fp<->uint, so expand them by llvm in initSPUActions()
225 /// Floating-point Ops { in initSPUActions()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp1 //===-- AArch64ISelLowering.cpp - AArch64 DAG Lowering Implementation ----===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
109 #define DEBUG_TYPE "aarch64-lower"
119 "aarch64-elf-ldtls-generation", cl::Hidden,
124 EnableOptimizeLogicalImm("aarch64-enable-logical-imm", cl::Hidden,
134 EnableCombineMGatherIntrinsics("aarch64-enable-mgather-combine", cl::Hidden,
139 static cl::opt<bool> EnableExtToTBL("aarch64-enable-ext-to-tbl", cl::Hidden,
146 static cl::opt<unsigned> MaxXors("aarch64-max-xors", cl::init(16), cl::Hidden,
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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1 //=- LoongArchISelLowering.cpp - LoongArch DAG Lowering Implementation ---===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
37 #define DEBUG_TYPE "loongarch-isel-lowering"
41 static cl::opt<bool> ZeroDivCheck("loongarch-check-zero-division", cl::Hidden,
102 // Expand bitreverse.i16 with native-width bitrev and shift for now, before in LoongArchTargetLowering()
107 // LA32 does not have REVB.2W and REVB.D due to the 64-bit operands, and in LoongArchTargetLowering()
109 // and i32 could still be byte-swapped relatively cheaply. in LoongArchTargetLowering()
178 setOperationAction(ISD::FSIN, MVT::f32, Expand); in LoongArchTargetLowering()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
122 #define DEBUG_TYPE "arm-isel"
131 ARMInterworking("arm-interworking", cl::Hidden,
136 "arm-promote-constant", cl::Hidden,
141 "arm-promote-constant-max-size", cl::Hidden,
145 "arm-promote-constant-max-total", cl::Hidden,
150 MVEMaxSupportedInterleaveFactor("mve-max-interleave-factor", cl::Hidden,
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/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1 //===-- NVPTXISelLowering.cpp - NVPTX DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
69 #define DEBUG_TYPE "nvptx-lower"
76 "nvptx-sched4reg",
80 "nvptx-fma-level", cl::Hidden,
86 "nvptx-prec-divf32", cl::Hidden,
92 "nvptx-prec-sqrtf32", cl::Hidden,
97 "nvptx-force-min-byval-param-align", cl::Hidden,
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