Lines Matching +full:fsin +full:- +full:output
1 //===-- VEISelLowering.cpp - VE DAG Lowering Implementation ---------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
39 #define DEBUG_TYPE "ve-lower"
41 //===----------------------------------------------------------------------===//
43 //===----------------------------------------------------------------------===//
91 if (Subtarget->enableVPU()) { in initRegisterClasses()
212 // VE doesn't have instructions for fp<->uint, so expand them by llvm in initSPUActions()
225 /// Floating-point Ops { in initSPUActions()
226 /// Note: Floating-point operations are fneg, fadd, fsub, fmul, fdiv, frem, in initSPUActions()
242 /// } Floating-point Ops in initSPUActions()
244 /// Floating-point math functions { in initSPUActions()
253 setOperationAction(ISD::FSIN, VT, Expand); in initSPUActions()
262 /// } Floating-point math functions in initSPUActions()
322 // TODO We will custom-widen into VVP_* nodes in the future. While we are in initVPUActions()
372 // CCValAssign - represent the assignment of the return value to locations. in LowerReturn()
375 // CCState - Info about the registers and stack slot. in LowerReturn()
385 // Copy the result values into the output registers. in LowerReturn()
408 // +------+------+ in LowerReturn()
410 // +------+------+ in LowerReturn()
448 unsigned ArgsBaseOffset = Subtarget->getRsaSize(); in LowerFormalArguments()
468 // Create a virtual register for the promoted live-in value. in LowerFormalArguments()
487 // +------+------+ in LowerFormalArguments()
489 // +------+------+ in LowerFormalArguments()
524 // +------+------+ in LowerFormalArguments()
526 // +------+------+ in LowerFormalArguments()
541 // in registers %s0-%s8. in LowerFormalArguments()
549 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgsBaseOffset); in LowerFormalArguments()
576 //===----------------------------------------------------------------------===//
578 //===----------------------------------------------------------------------===//
591 unsigned ArgsBaseOffset = Subtarget->getRsaSize(); in LowerCall()
605 // VE requires to use both register and stack for varargs or no-prototyped in LowerCall()
619 // Keep stack frames 16-byte aligned. in LowerCall()
642 // Likewise ExternalSymbol -> TargetExternalSymbol. in LowerCall()
647 // PC-relative references to external symbols should go through $stub. in LowerCall()
653 GV = CalleeG->getGlobal(); in LowerCall()
663 Subtarget->getInstrInfo()->getGlobalBaseReg(&MF); in LowerCall()
673 Subtarget->getInstrInfo()->getGlobalBaseReg(&MF); in LowerCall()
674 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, 0); in LowerCall()
706 // +------+------+ in LowerCall()
708 // +------+------+ in LowerCall()
762 // Add a register mask operand representing the call-preserved registers. in LowerCall()
763 const VERegisterInfo *TRI = Subtarget->getRegisterInfo(); in LowerCall()
765 TRI->getCallPreservedMask(DAG.getMachineFunction(), CLI.CallConv); in LowerCall()
809 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall()
833 // +------+------+ in LowerCall()
835 // +------+------+ in LowerCall()
867 /// isFPImmLegal - Returns true if the target can instruction select the
913 // We have target-specific dag combine patterns for the following nodes: in VETargetLowering()
924 computeRegisterProperties(Subtarget->getRegisterInfo()); in VETargetLowering()
977 return DAG.getTargetGlobalAddress(GA->getGlobal(), SDLoc(GA), in withTargetFlags()
978 GA->getValueType(0), GA->getOffset(), TF); in withTargetFlags()
981 return DAG.getTargetBlockAddress(BA->getBlockAddress(), Op.getValueType(), in withTargetFlags()
985 return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0), in withTargetFlags()
986 CP->getAlign(), CP->getOffset(), TF); in withTargetFlags()
989 return DAG.getTargetExternalSymbol(ES->getSymbol(), ES->getValueType(0), in withTargetFlags()
993 return DAG.getTargetJumpTable(JT->getIndex(), JT->getValueType(0), TF); in withTargetFlags()
1020 (GlobalN && GlobalN->getGlobal()->hasLocalLinkage())) { in makeAddress()
1065 llvm_unreachable("Invalid fence: unordered/non-atomic"); in emitLeadingFence()
1073 if (!Inst->hasAtomicStore()) in emitLeadingFence()
1086 llvm_unreachable("Invalid fence: unordered/not-atomic"); in emitTrailingFence()
1108 // cross-thread fence. in lowerATOMIC_FENCE()
1140 // MEMBARRIER is a compiler barrier; it codegens to a no-op. in lowerATOMIC_FENCE()
1147 if (AI->getOperation() == AtomicRMWInst::Xchg) { in shouldExpandAtomicRMWInIR()
1161 SDValue Ptr = N->getOperand(1); in prepareTS1AM()
1162 SDValue Val = N->getOperand(2); in prepareTS1AM()
1164 bool Byte = N->getMemoryVT() == MVT::i8; in prepareTS1AM()
1183 bool Byte = cast<AtomicSDNode>(Op)->getMemoryVT() == MVT::i8; in finalizeTS1AM()
1198 if (N->getMemoryVT() == MVT::i8) { in lowerATOMIC_SWAP()
1203 // Output: in lowerATOMIC_SWAP()
1209 // Aligned = AND Ptr, -4 in lowerATOMIC_SWAP()
1218 SDValue Ptr = N->getOperand(1); in lowerATOMIC_SWAP()
1220 {Ptr, DAG.getConstant(-4, DL, MVT::i64)}); in lowerATOMIC_SWAP()
1221 SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(), in lowerATOMIC_SWAP()
1222 DAG.getVTList(Op.getNode()->getValueType(0), in lowerATOMIC_SWAP()
1223 Op.getNode()->getValueType(1)), in lowerATOMIC_SWAP()
1224 {N->getChain(), Aligned, Flag, NewVal}, in lowerATOMIC_SWAP()
1225 N->getMemOperand()); in lowerATOMIC_SWAP()
1231 if (N->getMemoryVT() == MVT::i16) { in lowerATOMIC_SWAP()
1237 SDValue Ptr = N->getOperand(1); in lowerATOMIC_SWAP()
1239 {Ptr, DAG.getConstant(-4, DL, MVT::i64)}); in lowerATOMIC_SWAP()
1240 SDValue TS1AM = DAG.getAtomic(VEISD::TS1AM, DL, N->getMemoryVT(), in lowerATOMIC_SWAP()
1241 DAG.getVTList(Op.getNode()->getValueType(0), in lowerATOMIC_SWAP()
1242 Op.getNode()->getValueType(1)), in lowerATOMIC_SWAP()
1243 {N->getChain(), Aligned, Flag, NewVal}, in lowerATOMIC_SWAP()
1244 N->getMemOperand()); in lowerATOMIC_SWAP()
1286 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask( in lowerToTLSGeneralDynamicModel()
1301 Subtarget->getInstrInfo()->getGlobalBaseReg(&MF); in lowerToTLSGeneralDynamicModel()
1310 // code described in VE-tls_v1.1.pdf (*1) as its input. Instead, we always in lowerGlobalTLSAddress()
1313 // *1: https://www.nec.com/en/global/prod/hpc/aurora/document/VE-tls_v1.1.pdf in lowerGlobalTLSAddress()
1325 assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type"); in lowerLoadF128()
1326 Align Alignment = LdNode->getAlign(); in lowerLoadF128()
1331 DAG.getLoad(MVT::f64, DL, LdNode->getChain(), LdNode->getBasePtr(), in lowerLoadF128()
1332 LdNode->getPointerInfo(), Alignment, in lowerLoadF128()
1333 LdNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerLoadF128()
1335 EVT AddrVT = LdNode->getBasePtr().getValueType(); in lowerLoadF128()
1336 SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, LdNode->getBasePtr(), in lowerLoadF128()
1339 DAG.getLoad(MVT::f64, DL, LdNode->getChain(), HiPtr, in lowerLoadF128()
1340 LdNode->getPointerInfo(), Alignment, in lowerLoadF128()
1341 LdNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerLoadF128()
1370 assert(LdNode && LdNode->getOffset().isUndef() && "Unexpected node type"); in lowerLoadI1()
1372 SDValue BasePtr = LdNode->getBasePtr(); in lowerLoadI1()
1373 Align Alignment = LdNode->getAlign(); in lowerLoadI1()
1378 EVT MemVT = LdNode->getMemoryVT(); in lowerLoadI1()
1387 DAG.getLoad(MVT::i64, DL, LdNode->getChain(), Addr, in lowerLoadI1()
1388 LdNode->getPointerInfo(), Alignment, in lowerLoadI1()
1389 LdNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerLoadI1()
1408 DAG.getLoad(MVT::i64, DL, LdNode->getChain(), Addr, in lowerLoadI1()
1409 LdNode->getPointerInfo(), Alignment, in lowerLoadI1()
1410 LdNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerLoadI1()
1429 EVT MemVT = LdNode->getMemoryVT(); in lowerLOAD()
1431 // If VPU is enabled, always expand non-mask vector loads to VVP in lowerLOAD()
1432 if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(MemVT)) in lowerLOAD()
1435 SDValue BasePtr = LdNode->getBasePtr(); in lowerLOAD()
1454 assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type"); in lowerStoreF128()
1460 StNode->getValue(), SubRegEven); in lowerStoreF128()
1462 StNode->getValue(), SubRegOdd); in lowerStoreF128()
1464 Align Alignment = StNode->getAlign(); in lowerStoreF128()
1471 DAG.getStore(StNode->getChain(), DL, SDValue(Lo64, 0), in lowerStoreF128()
1472 StNode->getBasePtr(), MachinePointerInfo(), Alignment, in lowerStoreF128()
1473 StNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerStoreF128()
1475 EVT AddrVT = StNode->getBasePtr().getValueType(); in lowerStoreF128()
1476 SDValue HiPtr = DAG.getNode(ISD::ADD, DL, AddrVT, StNode->getBasePtr(), in lowerStoreF128()
1479 DAG.getStore(StNode->getChain(), DL, SDValue(Hi64, 0), HiPtr, in lowerStoreF128()
1481 StNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerStoreF128()
1495 assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type"); in lowerStoreI1()
1497 SDValue BasePtr = StNode->getBasePtr(); in lowerStoreI1()
1498 Align Alignment = StNode->getAlign(); in lowerStoreI1()
1502 EVT MemVT = StNode->getMemoryVT(); in lowerStoreI1()
1507 DAG.getMachineNode(VE::SVMmi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1512 DAG.getStore(StNode->getChain(), DL, SDValue(V, 0), Addr, in lowerStoreI1()
1514 StNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerStoreI1()
1522 DAG.getMachineNode(VE::SVMyi, DL, MVT::i64, StNode->getValue(), in lowerStoreI1()
1527 DAG.getStore(StNode->getChain(), DL, SDValue(V, 0), Addr, in lowerStoreI1()
1529 StNode->isVolatile() ? MachineMemOperand::MOVolatile in lowerStoreI1()
1541 assert(StNode && StNode->getOffset().isUndef() && "Unexpected node type"); in lowerSTORE()
1542 EVT MemVT = StNode->getMemoryVT(); in lowerSTORE()
1544 // If VPU is enabled, always expand non-mask vector stores to VVP in lowerSTORE()
1545 if (Subtarget->enableVPU() && MemVT.isVector() && !isMaskType(MemVT)) in lowerSTORE()
1548 SDValue BasePtr = StNode->getBasePtr(); in lowerSTORE()
1577 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL)); in lowerVASTART()
1578 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); in lowerVASTART()
1585 EVT VT = Node->getValueType(0); in lowerVAARG()
1586 SDValue InChain = Node->getOperand(0); in lowerVAARG()
1587 SDValue VAListPtr = Node->getOperand(1); in lowerVAARG()
1589 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); in lowerVAARG()
1602 DAG.getConstant(Align - 1, DL, PtrVT)); in lowerVAARG()
1604 DAG.getConstant(-Align, DL, PtrVT)); in lowerVAARG()
1609 // float --> need special handling like below. in lowerVAARG()
1611 // +------+------+ in lowerVAARG()
1613 // +------+------+ in lowerVAARG()
1649 EVT VT = Node->getValueType(0); in lowerDYNAMIC_STACKALLOC()
1655 const TargetFrameLowering &TFI = *Subtarget->getFrameLowering(); in lowerDYNAMIC_STACKALLOC()
1666 Entry.Node = DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT); in lowerDYNAMIC_STACKALLOC()
1690 DAG.getConstant((Alignment->value() - 1ULL), DL, VT)); in lowerDYNAMIC_STACKALLOC()
1692 DAG.getConstant(~(Alignment->value() - 1ULL), DL, VT)); in lowerDYNAMIC_STACKALLOC()
1734 const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo(); in lowerFRAMEADDR()
1735 Register FrameReg = RegInfo->getFrameRegister(MF); in lowerFRAMEADDR()
1738 while (Depth--) in lowerFRAMEADDR()
1780 TM->getStrList()->push_back(std::string( in lowerINTRINSIC_WO_CHAIN()
1783 DAG.getTargetExternalSymbol(TM->getStrList()->back().c_str(), VT, 0); in lowerINTRINSIC_WO_CHAIN()
1800 // Find first non-undef insertion. in getUniqueInsertion()
1802 for (Idx = 0; Idx < BVN->getNumOperands(); ++Idx) { in getUniqueInsertion()
1803 auto ElemV = BVN->getOperand(Idx); in getUniqueInsertion()
1804 if (!ElemV->isUndef()) in getUniqueInsertion()
1807 // Catch the (hypothetical) all-undef case. in getUniqueInsertion()
1808 if (Idx == BVN->getNumOperands()) in getUniqueInsertion()
1813 for (; Idx < BVN->getNumOperands(); ++Idx) { in getUniqueInsertion()
1814 auto ElemV = BVN->getOperand(Idx); in getUniqueInsertion()
1815 if (!ElemV->isUndef()) in getUniqueInsertion()
1823 return BuildVec->getSplatValue(); in getSplatValue()
1837 auto ElemV = Op->getOperand(UniqueIdx); in lowerBUILD_VECTOR()
1855 // Custom legalization on VVP_* and VEC_* opcodes is required to pack-legalize in getCustomOperationAction()
1859 // Packing opcodes are created with a pack-legal AVL (LEGALAVL). No need to in getCustomOperationAction()
1860 // re-visit them. in getCustomOperationAction()
1953 switch (N->getOpcode()) { in ReplaceNodeResults()
1958 LLVM_DEBUG(N->dumpr(&DAG)); in ReplaceNodeResults()
1968 /// .4byte .LBB0_2-.LJTI0_0
1971 /// .4byte .LBB0_2-<function name>
1988 // .4bytes .LBB0_2-<function name> in LowerCustomJumpTableEntry()
1989 const auto *Value = MCSymbolRefExpr::create(MBB->getSymbol(), Ctx); in LowerCustomJumpTableEntry()
1990 MCSymbol *Sym = Ctx.getOrCreateSymbol(MBB->getParent()->getName().data()); in LowerCustomJumpTableEntry()
2001 auto PtrTy = getPointerTy(DAG.getDataLayout(), Function->getAddressSpace()); in getPICJumpTableRelocBase()
2004 // .4bytes .LBB0_2-<function name> in getPICJumpTableRelocBase()
2025 MachineRegisterInfo &MRI = MF->getRegInfo(); in prepareMBB()
2026 const VEInstrInfo *TII = Subtarget->getInstrInfo(); in prepareMBB()
2038 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2042 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2045 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareMBB()
2050 // Create following instructions for non-PIC code. in prepareMBB()
2054 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareMBB()
2058 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareMBB()
2061 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareMBB()
2075 MachineRegisterInfo &MRI = MF->getRegInfo(); in prepareSymbol()
2076 const VEInstrInfo *TII = Subtarget->getInstrInfo(); in prepareSymbol()
2083 // Create following instructions for non-local linkage PIC code function in prepareSymbol()
2084 // calls. These instructions uses IC and magic number -24, so we expand in prepareSymbol()
2086 // lea %Reg, Symbol@plt_lo(-24) in prepareSymbol()
2090 BuildMI(MBB, I, DL, TII->get(VE::GETFUNPLT), Result) in prepareSymbol()
2099 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2103 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2106 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Result) in prepareSymbol()
2119 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2123 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2126 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3) in prepareSymbol()
2130 BuildMI(MBB, I, DL, TII->get(VE::LDrii), Result) in prepareSymbol()
2138 // Create following instructions for non-PIC code. in prepareSymbol()
2142 BuildMI(MBB, I, DL, TII->get(VE::LEAzii), Tmp1) in prepareSymbol()
2146 BuildMI(MBB, I, DL, TII->get(VE::ANDrm), Tmp2) in prepareSymbol()
2149 BuildMI(MBB, I, DL, TII->get(VE::LEASLrii), Result) in prepareSymbol()
2162 const VEInstrInfo *TII = Subtarget->getInstrInfo(); in setupEntryBlockForSjLj()
2169 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in setupEntryBlockForSjLj()
2178 MachineFunction *MF = MBB->getParent(); in emitEHSjLjSetJmp()
2179 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in emitEHSjLjSetJmp()
2180 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); in emitEHSjLjSetJmp()
2181 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitEHSjLjSetJmp()
2183 const BasicBlock *BB = MBB->getBasicBlock(); in emitEHSjLjSetJmp()
2184 MachineFunction::iterator I = ++MBB->getIterator(); in emitEHSjLjSetJmp()
2195 assert(TRI->isTypeLegalForClass(*RC, MVT::i32) && "Invalid destination!"); in emitEHSjLjSetJmp()
2221 MachineBasicBlock *MainMBB = MF->CreateMachineBasicBlock(BB); in emitEHSjLjSetJmp()
2222 MachineBasicBlock *SinkMBB = MF->CreateMachineBasicBlock(BB); in emitEHSjLjSetJmp()
2223 MachineBasicBlock *RestoreMBB = MF->CreateMachineBasicBlock(BB); in emitEHSjLjSetJmp()
2224 MF->insert(I, MainMBB); in emitEHSjLjSetJmp()
2225 MF->insert(I, SinkMBB); in emitEHSjLjSetJmp()
2226 MF->push_back(RestoreMBB); in emitEHSjLjSetJmp()
2227 RestoreMBB->setMachineBlockAddressTaken(); in emitEHSjLjSetJmp()
2230 SinkMBB->splice(SinkMBB->begin(), MBB, in emitEHSjLjSetJmp()
2231 std::next(MachineBasicBlock::iterator(MI)), MBB->end()); in emitEHSjLjSetJmp()
2232 SinkMBB->transferSuccessorsAndUpdatePHIs(MBB); in emitEHSjLjSetJmp()
2239 const VEFrameLowering *TFI = Subtarget->getFrameLowering(); in emitEHSjLjSetJmp()
2240 if (TFI->hasBP(*MF)) { in emitEHSjLjSetJmp()
2241 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2250 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(VE::STrii)); in emitEHSjLjSetJmp()
2261 BuildMI(*ThisMBB, MI, DL, TII->get(VE::EH_SjLj_Setup)).addMBB(RestoreMBB); in emitEHSjLjSetJmp()
2263 const VERegisterInfo *RegInfo = Subtarget->getRegisterInfo(); in emitEHSjLjSetJmp()
2264 MIB.addRegMask(RegInfo->getNoPreservedMask()); in emitEHSjLjSetJmp()
2265 ThisMBB->addSuccessor(MainMBB); in emitEHSjLjSetJmp()
2266 ThisMBB->addSuccessor(RestoreMBB); in emitEHSjLjSetJmp()
2269 BuildMI(MainMBB, DL, TII->get(VE::LEAzii), MainDestReg) in emitEHSjLjSetJmp()
2273 MainMBB->addSuccessor(SinkMBB); in emitEHSjLjSetJmp()
2276 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(VE::PHI), DstReg) in emitEHSjLjSetJmp()
2286 if (TFI->hasBP(*MF)) { in emitEHSjLjSetJmp()
2288 BuildMI(RestoreMBB, DL, TII->get(VE::LDrii), VE::SX17); in emitEHSjLjSetJmp()
2294 BuildMI(RestoreMBB, DL, TII->get(VE::LEAzii), RestoreDestReg) in emitEHSjLjSetJmp()
2298 BuildMI(RestoreMBB, DL, TII->get(VE::BRCFLa_t)).addMBB(SinkMBB); in emitEHSjLjSetJmp()
2299 RestoreMBB->addSuccessor(SinkMBB); in emitEHSjLjSetJmp()
2309 MachineFunction *MF = MBB->getParent(); in emitEHSjLjLongJmp()
2310 const TargetInstrInfo *TII = Subtarget->getInstrInfo(); in emitEHSjLjLongJmp()
2311 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitEHSjLjLongJmp()
2337 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), FP); in emitEHSjLjLongJmp()
2344 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), Tmp); in emitEHSjLjLongJmp()
2352 BuildMI(*ThisMBB, MI, DL, TII->get(VE::ORri), VE::SX10) in emitEHSjLjLongJmp()
2357 MIB = BuildMI(*ThisMBB, MI, DL, TII->get(VE::LDrii), SP); in emitEHSjLjLongJmp()
2364 BuildMI(*ThisMBB, MI, DL, TII->get(VE::BCFLari_t)) in emitEHSjLjLongJmp()
2376 MachineFunction *MF = BB->getParent(); in emitSjLjDispatchBlock()
2377 MachineFrameInfo &MFI = MF->getFrameInfo(); in emitSjLjDispatchBlock()
2378 MachineRegisterInfo &MRI = MF->getRegInfo(); in emitSjLjDispatchBlock()
2379 const VEInstrInfo *TII = Subtarget->getInstrInfo(); in emitSjLjDispatchBlock()
2400 if (!MF->hasCallSiteLandingPad(Sym)) in emitSjLjDispatchBlock()
2403 for (unsigned CSI : MF->getCallSiteLandingPad(Sym)) { in emitSjLjDispatchBlock()
2417 InvokeBBs.insert(LP->pred_begin(), LP->pred_end()); in emitSjLjDispatchBlock()
2424 // The %fn_context is allocated like below (from --print-after=sjljehprepare): in emitSjLjDispatchBlock()
2452 MachineBasicBlock *DispatchBB = MF->CreateMachineBasicBlock(); in emitSjLjDispatchBlock()
2453 DispatchBB->setIsEHPad(true); in emitSjLjDispatchBlock()
2456 MachineBasicBlock *TrapBB = MF->CreateMachineBasicBlock(); in emitSjLjDispatchBlock()
2457 DispatchBB->addSuccessor(TrapBB); in emitSjLjDispatchBlock()
2459 MachineBasicBlock *DispContBB = MF->CreateMachineBasicBlock(); in emitSjLjDispatchBlock()
2460 DispatchBB->addSuccessor(DispContBB); in emitSjLjDispatchBlock()
2463 MF->push_back(DispatchBB); in emitSjLjDispatchBlock()
2464 MF->push_back(DispContBB); in emitSjLjDispatchBlock()
2465 MF->push_back(TrapBB); in emitSjLjDispatchBlock()
2468 Register Abort = prepareSymbol(*TrapBB, TrapBB->end(), "abort", DL, in emitSjLjDispatchBlock()
2470 BuildMI(TrapBB, DL, TII->get(VE::BSICrii), VE::SX10) in emitSjLjDispatchBlock()
2481 MachineJumpTableInfo *JTI = MF->getOrCreateJumpTableInfo(JTE); in emitSjLjDispatchBlock()
2482 unsigned MJTI = JTI->createJumpTableIndex(LPadList); in emitSjLjDispatchBlock()
2484 const VERegisterInfo &RI = TII->getRegisterInfo(); in emitSjLjDispatchBlock()
2487 BuildMI(DispatchBB, DL, TII->get(VE::NOP)) in emitSjLjDispatchBlock()
2493 BuildMI(DispatchBB, DL, TII->get(VE::GETGOT), VE::SX15); in emitSjLjDispatchBlock()
2499 addFrameReference(BuildMI(DispatchBB, DL, TII->get(VE::LDLZXrii), IReg), FI, in emitSjLjDispatchBlock()
2502 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLir_t)) in emitSjLjDispatchBlock()
2510 BuildMI(DispatchBB, DL, TII->get(VE::LEAzii), TmpReg) in emitSjLjDispatchBlock()
2514 BuildMI(DispatchBB, DL, TII->get(VE::BRCFLrr_t)) in emitSjLjDispatchBlock()
2530 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2534 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2537 BuildMI(DispContBB, DL, TII->get(VE::LEASLrri), BReg) in emitSjLjDispatchBlock()
2542 // Create following instructions for non-PIC code. in emitSjLjDispatchBlock()
2546 BuildMI(DispContBB, DL, TII->get(VE::LEAzii), Tmp1) in emitSjLjDispatchBlock()
2550 BuildMI(DispContBB, DL, TII->get(VE::ANDrm), Tmp2) in emitSjLjDispatchBlock()
2553 BuildMI(DispContBB, DL, TII->get(VE::LEASLrii), BReg) in emitSjLjDispatchBlock()
2561 // Generate simple block address code for no-PIC model. in emitSjLjDispatchBlock()
2569 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2572 BuildMI(DispContBB, DL, TII->get(VE::LDrri), TReg) in emitSjLjDispatchBlock()
2576 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2595 BuildMI(DispContBB, DL, TII->get(VE::SLLri), Tmp1) in emitSjLjDispatchBlock()
2598 BuildMI(DispContBB, DL, TII->get(VE::LDLZXrri), OReg) in emitSjLjDispatchBlock()
2603 prepareSymbol(*DispContBB, DispContBB->end(), in emitSjLjDispatchBlock()
2604 DispContBB->getParent()->getName(), DL, /* Local */ true); in emitSjLjDispatchBlock()
2605 BuildMI(DispContBB, DL, TII->get(VE::ADDSLrr), TReg) in emitSjLjDispatchBlock()
2608 BuildMI(DispContBB, DL, TII->get(VE::BCFLari_t)) in emitSjLjDispatchBlock()
2621 DispContBB->addSuccessor(LP); in emitSjLjDispatchBlock()
2625 const MCPhysReg *SavedRegs = MF->getRegInfo().getCalleeSavedRegs(); in emitSjLjDispatchBlock()
2630 SmallVector<MachineBasicBlock *, 8> Successors(MBB->succ_rbegin(), in emitSjLjDispatchBlock()
2631 MBB->succ_rend()); in emitSjLjDispatchBlock()
2634 if (MBBS->isEHPad()) { in emitSjLjDispatchBlock()
2635 MBB->removeSuccessor(MBBS); in emitSjLjDispatchBlock()
2640 MBB->addSuccessor(DispatchBB); in emitSjLjDispatchBlock()
2642 // Find the invoke call and mark all of the callee-saved registers as in emitSjLjDispatchBlock()
2666 // Mark all former landing pads as non-landing pads. The dispatch is the only in emitSjLjDispatchBlock()
2669 LP->setIsEHPad(false); in emitSjLjDispatchBlock()
2698 return isInt<7>(C->getSExtValue()); in isSimm7()
2702 const APInt &Imm = C->getValueAPF().bitcastToAPInt(); in isSimm7()
2753 // or general comparison with -enable-no-nans-fp-math option reach in safeWithoutCompWithNull()
2789 assert(N->getOpcode() == ISD::SELECT && in combineSelect()
2792 SDValue Cond = N->getOperand(0); in combineSelect()
2793 SDValue True = N->getOperand(1); in combineSelect()
2794 SDValue False = N->getOperand(2); in combineSelect()
2797 EVT VT = N->getValueType(0); in combineSelect()
2830 assert(N->getOpcode() == ISD::SELECT_CC && in combineSelectCC()
2832 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in combineSelectCC()
2833 SDValue LHS = N->getOperand(0); in combineSelectCC()
2834 SDValue RHS = N->getOperand(1); in combineSelectCC()
2835 SDValue True = N->getOperand(2); in combineSelectCC()
2836 SDValue False = N->getOperand(3); in combineSelectCC()
2839 EVT VT = N->getValueType(0); in combineSelectCC()
2898 switch (User->getOpcode()) { in isI32Insn()
2922 if (N->getOperand(0).getOpcode() != ISD::SRL) in isI32Insn()
2928 if (User->getOperand(2).getNode() != N && in isI32Insn()
2929 User->getOperand(3).getNode() != N) in isI32Insn()
2933 // CMOV in (cmov (trunc ...), true, false, int-comparison) is safe. in isI32Insn()
2935 if (User->getOperand(1).getNode() != N && in isI32Insn()
2936 User->getOperand(2).getNode() != N && in isI32Insn()
2937 isa<ConstantSDNode>(User->getOperand(3))) { in isI32Insn()
2939 static_cast<VECC::CondCode>(User->getConstantOperandVal(3)); in isI32Insn()
2957 for (const SDNode *U : User->uses()) { in isI32InsnAllUses()
2958 switch (U->getOpcode()) { in isI32InsnAllUses()
2972 assert(N->getValueType(0) == MVT::i32 && in isI32InsnAllUses()
2974 if (User->getOpcode() == ISD::SELECT_CC || in isI32InsnAllUses()
2975 User->getOpcode() == ISD::SELECT || User->getOpcode() == VEISD::CMOV) in isI32InsnAllUses()
2990 assert(N->getOpcode() == ISD::TRUNCATE && in combineTRUNCATE()
2995 EVT VT = N->getValueType(0); in combineTRUNCATE()
3002 if (N->getOperand(0)->getOpcode() == ISD::SELECT_CC && in combineTRUNCATE()
3003 isa<ConstantSDNode>(N->getOperand(0)->getOperand(0)) && in combineTRUNCATE()
3004 isa<ConstantSDNode>(N->getOperand(0)->getOperand(1))) in combineTRUNCATE()
3008 for (const SDNode *User : N->uses()) { in combineTRUNCATE()
3023 N->getOperand(0), SubI32), in combineTRUNCATE()
3029 switch (N->getOpcode()) { in PerformDAGCombine()
3043 //===----------------------------------------------------------------------===//
3045 //===----------------------------------------------------------------------===//
3082 //===----------------------------------------------------------------------===//
3084 //===----------------------------------------------------------------------===//
3103 // function is used to check whether an immediate value is OK for and-not in hasAndNot()
3135 if (false /* Idx->isConstant() */) { in lowerEXTRACT_VECTOR_ELT()
3193 if (false /* Idx->isConstant()*/) { in lowerINSERT_VECTOR_ELT()