Lines Matching +full:fsin +full:- +full:output
1 //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
40 //===----------------------------------------------------------------------===//
42 //===----------------------------------------------------------------------===//
106 // Allocate a full-sized argument for the 64-bit ABI.
112 "Can't handle non-64 bits locations"); in Analyze_CC_Sparc64_Full()
121 // Promote integers to %i0-%i5. in Analyze_CC_Sparc64_Full()
124 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). in Analyze_CC_Sparc64_Full()
130 // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7). in Analyze_CC_Sparc64_Full()
144 // This argument goes on the stack in an 8-byte slot. in Analyze_CC_Sparc64_Full()
146 // the right-aligned float. The first 4 bytes of the stack slot are undefined. in Analyze_CC_Sparc64_Full()
154 // Allocate a half-sized argument for the 64-bit ABI.
160 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); in Analyze_CC_Sparc64_Half()
164 // Promote floats to %f0-%f31. in Analyze_CC_Sparc64_Half()
171 // Promote integers to %i0-%i5, using half the register. in Analyze_CC_Sparc64_Half()
231 return Reg - SP::I0 + SP::O0; in toCallerWindow()
240 return CCInfo.CheckReturn(Outs, Subtarget->is64Bit() ? RetCC_Sparc64 in CanLowerReturn()
250 if (Subtarget->is64Bit()) in LowerReturn()
263 // CCValAssign - represent the assignment of the return value to locations. in LowerReturn_32()
266 // CCState - Info about the registers and stack slot. in LowerReturn_32()
278 // Copy the result values into the output registers. in LowerReturn_32()
289 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would in LowerReturn_32()
317 Register Reg = SFI->getSRetReturnReg(); in LowerReturn_32()
338 // Lower return values for the 64-bit ABI.
346 // CCValAssign - represent the assignment of the return value to locations. in LowerReturn_64()
349 // CCState - Info about the registers and stack slot. in LowerReturn_64()
360 // The return address is always %i7+8 with the 64-bit ABI. in LowerReturn_64()
363 // Copy the result values into the output registers. in LowerReturn_64()
421 if (Subtarget->is64Bit()) in LowerFormalArguments()
428 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
517 // If it is double-word aligned, just load. in LowerFormalArguments_32()
573 Register Reg = SFI->getSRetReturnReg(); in LowerFormalArguments_32()
576 SFI->setSRetReturnReg(Reg); in LowerFormalArguments_32()
598 FuncInfo->setVarArgsFrameOffset(ArgOffset); in LowerFormalArguments_32()
646 // Create a virtual register for the promoted live-in value. in LowerFormalArguments_64()
685 // Adjust offset for extended arguments, SPARC is big-endian. in LowerFormalArguments_64()
689 Offset += 8 - ValSize; in LowerFormalArguments_64()
701 // in registers %i0-%i5. Variable floating point arguments are never passed in LowerFormalArguments_64()
702 // in floating point registers. They go on %i0-%i5 or on the stack like in LowerFormalArguments_64()
710 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea + in LowerFormalArguments_64()
711 Subtarget->getStackPointerBias()); in LowerFormalArguments_64()
741 return TRI->isReservedReg(MF, r); in isAnyArgRegReserved()
745 return TRI->isReservedReg(MF, r); in isAnyArgRegReserved()
760 if (Subtarget->is64Bit()) in LowerCall()
768 return Call->hasFnAttr(Attribute::ReturnsTwice); in hasReturnsTwiceAttr()
772 CalleeFn = dyn_cast<Function>(G->getGlobal()); in hasReturnsTwiceAttr()
777 const char *CalleeName = E->getSymbol(); in hasReturnsTwiceAttr()
778 CalleeFn = M->getFunction(CalleeName); in hasReturnsTwiceAttr()
783 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice); in hasReturnsTwiceAttr()
786 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
794 // Do not tail call opt functions with "disable-tail-calls" attribute. in IsEligibleForTailCallOptimization()
795 if (Caller.getFnAttribute("disable-tail-calls").getValueAsString() == "true") in IsEligibleForTailCallOptimization()
799 // 64-bit targets have a slightly higher limit since the ABI requires in IsEligibleForTailCallOptimization()
801 unsigned StackSizeLimit = Subtarget->is64Bit() ? 48 : 0; in IsEligibleForTailCallOptimization()
819 // Lower a call for the 32-bit ABI.
847 // Keep stack frames 8-byte aligned. in LowerCall_32()
952 // if it is double-word aligned, just store. in LowerCall_32()
1039 // Build a sequence of copy-to-reg nodes chained together with token in LowerCall_32()
1056 // Likewise ExternalSymbol -> TargetExternalSymbol. in LowerCall_32()
1060 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); in LowerCall_32()
1062 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); in LowerCall_32()
1078 // Add a register mask operand representing the call-preserved registers. in LowerCall_32()
1079 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); in LowerCall_32()
1082 ? TRI->getRTCallPreservedMask(CallConv) in LowerCall_32()
1083 : TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv)); in LowerCall_32()
1161 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); in getRegisterByName()
1162 if (!TRI->isReservedReg(MF, Reg)) in getRegisterByName()
1177 // This function post-processes a CCValAssign array created by
1195 unsigned Offset = argSize * (VA.getLocReg() - firstReg); in fixupVariableFloatArgs()
1199 // This argument should go in %i0-%i5. in fixupVariableFloatArgs()
1207 // Full register, just bitconvert into i128 -- We will lower this into in fixupVariableFloatArgs()
1220 // Lower a call for the 64-bit ABI.
1246 // Keep stack frames 16-byte aligned. in LowerCall_64()
1303 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); in LowerCall_64()
1304 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; in LowerCall_64()
1364 Subtarget->getStackPointerBias() + in LowerCall_64()
1388 // Likewise ExternalSymbol -> TargetExternalSymbol. in LowerCall_64()
1394 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT, 0, TF); in LowerCall_64()
1396 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF); in LowerCall_64()
1406 // Add a register mask operand representing the call-preserved registers. in LowerCall_64()
1407 const SparcRegisterInfo *TRI = Subtarget->getRegisterInfo(); in LowerCall_64()
1409 ((hasReturnsTwice) ? TRI->getRTCallPreservedMask(CLI.CallConv) in LowerCall_64()
1410 : TRI->getCallPreservedMask(DAG.getMachineFunction(), in LowerCall_64()
1463 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) in LowerCall_64()
1503 //===----------------------------------------------------------------------===//
1505 //===----------------------------------------------------------------------===//
1508 if (AI->getOperation() == AtomicRMWInst::Xchg && in shouldExpandAtomicRMWInIR()
1509 AI->getType()->getPrimitiveSizeInBits() == 32) in shouldExpandAtomicRMWInIR()
1515 /// intCondCCodeToRcond - Convert a DAG integer condition code to a SPARC
1536 /// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
1554 /// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
1597 if (!Subtarget->useSoftFloat()) { in SparcTargetLowering()
1602 if (Subtarget->is64Bit()) { in SparcTargetLowering()
1605 // On 32bit sparc, we define a double-register 32bit register in SparcTargetLowering()
1606 // class, as well. This is modeled in LLVM as a 2-vector of i32. in SparcTargetLowering()
1679 if (Subtarget->is64Bit()) { in SparcTargetLowering()
1686 // Custom expand fp<->sint in SparcTargetLowering()
1692 // Custom Expand fp<->uint in SparcTargetLowering()
1739 if (Subtarget->is64Bit()) { in SparcTargetLowering()
1752 Subtarget->usePopc() ? Legal : Expand); in SparcTargetLowering()
1762 // Atomics are supported on SparcV9. 32-bit atomics are also in SparcTargetLowering()
1765 if (Subtarget->isV9()) { in SparcTargetLowering()
1766 // TODO: we _ought_ to be able to support 64-bit atomics on 32-bit sparcv9, in SparcTargetLowering()
1768 if (Subtarget->is64Bit()) in SparcTargetLowering()
1772 } else if (Subtarget->hasLeonCasa()) in SparcTargetLowering()
1787 if (Subtarget->is64Bit()) { in SparcTargetLowering()
1794 if (!Subtarget->isV9()) { in SparcTargetLowering()
1800 setOperationAction(ISD::FSIN , MVT::f128, Expand); in SparcTargetLowering()
1805 setOperationAction(ISD::FSIN , MVT::f64, Expand); in SparcTargetLowering()
1810 setOperationAction(ISD::FSIN , MVT::f32, Expand); in SparcTargetLowering()
1836 if (Subtarget->useSoftMulDiv()) { in SparcTargetLowering()
1852 if (Subtarget->is64Bit()) { in SparcTargetLowering()
1884 Subtarget->usePopc() ? Legal : Expand); in SparcTargetLowering()
1886 if (Subtarget->isV9() && Subtarget->hasHardQuad()) { in SparcTargetLowering()
1894 if (Subtarget->hasHardQuad()) { in SparcTargetLowering()
1902 if (Subtarget->isV9()) { in SparcTargetLowering()
1910 if (!Subtarget->is64Bit()) { in SparcTargetLowering()
1933 if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) { in SparcTargetLowering()
1951 } else if (!Subtarget->useSoftFloat()) { in SparcTargetLowering()
1972 if (Subtarget->fixAllFDIVSQRT()) { in SparcTargetLowering()
1979 if (Subtarget->hasNoFMULS()) { in SparcTargetLowering()
1984 if (!Subtarget->is64Bit()) in SparcTargetLowering()
1987 if (Subtarget->hasLeonCycleCounter()) in SparcTargetLowering()
1994 computeRegisterProperties(Subtarget->getRegisterInfo()); in SparcTargetLowering()
1998 return Subtarget->useSoftFloat(); in useSoftFloat()
2049 /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
2098 return DAG.getTargetGlobalAddress(GA->getGlobal(), in withTargetFlags()
2100 GA->getValueType(0), in withTargetFlags()
2101 GA->getOffset(), TF); in withTargetFlags()
2104 return DAG.getTargetConstantPool(CP->getConstVal(), CP->getValueType(0), in withTargetFlags()
2105 CP->getAlign(), CP->getOffset(), TF); in withTargetFlags()
2108 return DAG.getTargetBlockAddress(BA->getBlockAddress(), in withTargetFlags()
2114 return DAG.getTargetExternalSymbol(ES->getSymbol(), in withTargetFlags()
2115 ES->getValueType(0), TF); in withTargetFlags()
2141 PICLevel::Level picLevel = M->getPICLevel(); in makeAddress()
2216 const GlobalValue *GV = GA->getGlobal(); in LowerGlobalTLSAddress()
2250 const uint32_t *Mask = Subtarget->getRegisterInfo()->getCallPreservedMask( in LowerGlobalTLSAddress()
2324 if (ArgTy->isFP128Ty()) { in LowerF128_LibCallArg()
2354 if (RetTy->isFP128Ty()) { in LowerF128Op()
2361 if (!Subtarget->is64Bit()) { in LowerF128Op()
2370 assert(Op->getNumOperands() >= numArgs && "Not enough operands!"); in LowerF128Op()
2384 assert (RetTy->isFP128Ty() && "Unexpected return type!"); in LowerF128Op()
2398 bool is64Bit = Subtarget->is64Bit(); in LowerF128Compare()
2502 llvm_unreachable("fpextend with non-float operand!"); in LowerF128_FPEXTEND()
2520 llvm_unreachable("fpround to non-float!"); in LowerF128_FPROUND()
2625 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
2640 // On V9 processors running in 64-bit mode, if CC compares two `i64`s in LowerBR_CC()
2651 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. in LowerBR_CC()
2654 // Non-v9 targets don't have xcc. in LowerBR_CC()
2677 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
2690 // On V9 processors running in 64-bit mode, if CC compares two `i64`s in LowerSELECT_CC()
2740 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset(), DL)); in LowerVASTART()
2741 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); in LowerVASTART()
2748 EVT VT = Node->getValueType(0); in LowerVAARG()
2749 SDValue InChain = Node->getOperand(0); in LowerVAARG()
2750 SDValue VAListPtr = Node->getOperand(1); in LowerVAARG()
2752 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); in LowerVAARG()
2775 cast<ConstantSDNode>(Op.getOperand(2))->getMaybeAlignValue(); in LowerDYNAMIC_STACKALLOC()
2776 Align StackAlign = Subtarget->getFrameLowering()->getStackAlign(); in LowerDYNAMIC_STACKALLOC()
2777 EVT VT = Size->getValueType(0); in LowerDYNAMIC_STACKALLOC()
2780 // TODO: implement over-aligned alloca. (Note: also implies in LowerDYNAMIC_STACKALLOC()
2786 "over-aligned dynamic alloca not supported."); in LowerDYNAMIC_STACKALLOC()
2792 if (Subtarget->is64Bit()) { in LowerDYNAMIC_STACKALLOC()
2796 // that's only 4-byte aligned, not 8-byte aligned (the stack in LowerDYNAMIC_STACKALLOC()
2797 // pointer is 8-byte aligned). So, if the user asked for an 8-byte in LowerDYNAMIC_STACKALLOC()
2799 // bottom of the stack, instead of 92, to ensure 8-byte alignment. in LowerDYNAMIC_STACKALLOC()
2801 // That also means adding 4 to the size of the allocation -- in LowerDYNAMIC_STACKALLOC()
2802 // before applying the 8-byte rounding. Unfortunately, we the in LowerDYNAMIC_STACKALLOC()
2824 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain in LowerDYNAMIC_STACKALLOC()
2826 regSpillArea += Subtarget->getStackPointerBias(); in LowerDYNAMIC_STACKALLOC()
2851 unsigned stackBias = Subtarget->getStackPointerBias(); in getFRAMEADDR()
2861 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56; in getFRAMEADDR()
2863 while (depth--) { in getFRAMEADDR()
2868 if (Subtarget->is64Bit()) in getFRAMEADDR()
2907 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget, true); in LowerRETURNADDR()
2909 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60; in LowerRETURNADDR()
2921 assert(SrcReg64.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); in LowerF64Op()
2928 // Note: in little-endian, the floating-point value is stored in the in LowerF64Op()
2930 // bit is the highest-numbered (odd), rather than the in LowerF64Op()
2931 // lowest-numbered (even). in LowerF64Op()
2957 assert(LdNode->getOffset().isUndef() && "Unexpected node type"); in LowerF128Load()
2959 Align Alignment = commonAlignment(LdNode->getOriginalAlign(), 8); in LowerF128Load()
2962 DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LdNode->getBasePtr(), in LowerF128Load()
2963 LdNode->getPointerInfo(), Alignment); in LowerF128Load()
2964 EVT addrVT = LdNode->getBasePtr().getValueType(); in LowerF128Load()
2966 LdNode->getBasePtr(), in LowerF128Load()
2968 SDValue Lo64 = DAG.getLoad(MVT::f64, dl, LdNode->getChain(), LoPtr, in LowerF128Load()
2969 LdNode->getPointerInfo().getWithOffset(8), in LowerF128Load()
2998 EVT MemVT = LdNode->getMemoryVT(); in LowerLOAD()
3009 assert(StNode->getOffset().isUndef() && "Unexpected node type"); in LowerF128Store()
3017 StNode->getValue(), in LowerF128Store()
3022 StNode->getValue(), in LowerF128Store()
3025 Align Alignment = commonAlignment(StNode->getOriginalAlign(), 8); in LowerF128Store()
3029 DAG.getStore(StNode->getChain(), dl, SDValue(Hi64, 0), in LowerF128Store()
3030 StNode->getBasePtr(), StNode->getPointerInfo(), in LowerF128Store()
3032 EVT addrVT = StNode->getBasePtr().getValueType(); in LowerF128Store()
3034 StNode->getBasePtr(), in LowerF128Store()
3036 OutChains[1] = DAG.getStore(StNode->getChain(), dl, SDValue(Lo64, 0), LoPtr, in LowerF128Store()
3037 StNode->getPointerInfo().getWithOffset(8), in LowerF128Store()
3047 EVT MemVT = St->getMemoryVT(); in LowerSTORE()
3054 SDValue Val = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, St->getValue()); in LowerSTORE()
3056 St->getChain(), dl, Val, St->getBasePtr(), St->getPointerInfo(), in LowerSTORE()
3057 St->getOriginalAlign(), St->getMemOperand()->getFlags(), in LowerSTORE()
3058 St->getAAInfo()); in LowerSTORE()
3078 // (As with LowerF64Op, on little-endian, we need to negate the odd in LowerFNEGorFABS()
3206 assert(MulResult->use_empty() && "Illegally typed node still in use!"); in LowerUMULO_SMULO()
3213 if (isStrongerThanMonotonic(cast<AtomicSDNode>(Op)->getSuccessOrdering())) { in LowerATOMIC_LOAD_STORE()
3238 bool hasHardQuad = Subtarget->hasHardQuad(); in LowerOperation()
3239 bool isV9 = Subtarget->isV9(); in LowerOperation()
3240 bool is64Bit = Subtarget->is64Bit(); in LowerOperation()
3301 APInt V = C->getValueAPF().bitcastToAPInt(); in bitcastConstantFPToInt()
3312 SDValue Src = N->getOperand(0); in PerformBITCASTCombine()
3314 if (isa<ConstantFPSDNode>(Src) && N->getSimpleValueType(0) == MVT::v2i32 && in PerformBITCASTCombine()
3323 switch (N->getOpcode()) { in PerformDAGCombine()
3341 if (Subtarget->isV9()) in EmitInstrWithCustomInserter()
3353 if (Subtarget->isV9()) in EmitInstrWithCustomInserter()
3362 const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); in expandSelectCC()
3367 // triangle control-flow pattern. The incoming instruction knows the in expandSelectCC()
3377 const BasicBlock *LLVM_BB = BB->getBasicBlock(); in expandSelectCC()
3378 MachineFunction::iterator It = ++BB->getIterator(); in expandSelectCC()
3381 MachineFunction *F = BB->getParent(); in expandSelectCC()
3382 MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB); in expandSelectCC()
3383 MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB); in expandSelectCC()
3384 F->insert(It, IfFalseMBB); in expandSelectCC()
3385 F->insert(It, SinkMBB); in expandSelectCC()
3388 SinkMBB->splice(SinkMBB->begin(), ThisMBB, in expandSelectCC()
3389 std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end()); in expandSelectCC()
3390 SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB); in expandSelectCC()
3393 ThisMBB->addSuccessor(IfFalseMBB); in expandSelectCC()
3394 ThisMBB->addSuccessor(SinkMBB); in expandSelectCC()
3401 IfFalseMBB->addSuccessor(SinkMBB); in expandSelectCC()
3404 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI), in expandSelectCC()
3415 //===----------------------------------------------------------------------===//
3417 //===----------------------------------------------------------------------===//
3419 /// getConstraintType - Given a constraint letter, return the type of
3455 if (isInt<13>(C->getSExtValue())) in getSingleConstraintMatchWeight()
3463 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3479 if (isInt<13>(C->getSExtValue())) { in LowerAsmOperandForConstraint()
3480 Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op), in LowerAsmOperandForConstraint()
3507 else if (Subtarget->is64Bit()) in getRegForInlineAsmConstraint()
3536 StringRef RegName(Constraint.data() + 1, Constraint.size() - 2); in getRegForInlineAsmConstraint()
3544 // r0-r7 -> g0-g7 in getRegForInlineAsmConstraint()
3545 // r8-r15 -> o0-o7 in getRegForInlineAsmConstraint()
3546 // r16-r23 -> l0-l7 in getRegForInlineAsmConstraint()
3547 // r24-r31 -> i0-i7 in getRegForInlineAsmConstraint()
3576 // Force the use of I64Regs over IntRegs for 64-bit values. in getRegForInlineAsmConstraint()
3577 if (Subtarget->is64Bit() && VT == MVT::i64) { in getRegForInlineAsmConstraint()
3600 switch (N->getOpcode()) { in ReplaceNodeResults()
3607 if (N->getOperand(0).getValueType() != MVT::f128 in ReplaceNodeResults()
3608 || N->getValueType(0) != MVT::i64) in ReplaceNodeResults()
3610 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) in ReplaceNodeResults()
3620 assert(Subtarget->hasLeonCycleCounter()); in ReplaceNodeResults()
3621 SDValue Lo = DAG.getCopyFromReg(N->getOperand(0), dl, SP::ASR23, MVT::i32); in ReplaceNodeResults()
3626 Results.push_back(N->getOperand(0)); in ReplaceNodeResults()
3632 if (N->getValueType(0) != MVT::f128 in ReplaceNodeResults()
3633 || N->getOperand(0).getValueType() != MVT::i64) in ReplaceNodeResults()
3636 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) in ReplaceNodeResults()
3649 if (Ld->getValueType(0) != MVT::i64 || Ld->getMemoryVT() != MVT::i64) in ReplaceNodeResults()
3654 Ld->getExtensionType(), dl, MVT::v2i32, Ld->getChain(), in ReplaceNodeResults()
3655 Ld->getBasePtr(), Ld->getPointerInfo(), MVT::v2i32, in ReplaceNodeResults()
3656 Ld->getOriginalAlign(), Ld->getMemOperand()->getFlags(), in ReplaceNodeResults()
3657 Ld->getAAInfo()); in ReplaceNodeResults()
3669 if (!Subtarget->isTargetLinux()) in useLoadStackGuardNode()
3676 if (!Subtarget->isTargetLinux()) in insertSSPDeclarations()
3684 if (!Node->hasAnyUseOfValue(0)) in AdjustInstrPostInstrSelection()