Lines Matching +full:fsin +full:- +full:output

1 //===- X86InstrFPStack.td - FPU Instruction Set ------------*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
15 // Some 'special' instructions - expanded after instruction selection.
49 // "RFP64" or "RFP80" registers: traditional register files to reference 32-bit,
50 // 64-bit or 80-bit floating point values.  These sizes apply to the values,
66 // FpIf32, FpIf64 - Floating Point Pseudo Instruction template.
77 // Register op register -> register
87 // in where the 'r' goes in assembly output.
88 // These instructions cannot address 80-bit memory.
185 // FPBinary_rr just defines pseudo-instructions, no need to set a scheduling
434 // FST does not support 80-bit memory target; FSTP must be used.
640 // Operand-less floating-point instructions for the disassembler.
658 def FSIN : I<0xD9, MRM_FE, (outs), (ins), "fsin", []>;
686 //===----------------------------------------------------------------------===//
687 // Non-Instruction Patterns
688 //===----------------------------------------------------------------------===//
706 // Floating point constant -0.0 and -1.0
714 // FP extensions map onto simple pseudo-value conversions if they are to/from
723 // FP truncations map onto simple pseudo-value conversions if they are to/from
724 // the FP stack.  We have validated that only value-preserving truncations make