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/linux/drivers/gpu/drm/amd/display/dc/spl/
H A Dspl_fixpt31_32.c1 // SPDX-License-Identifier: MIT
17 return (unsigned long long)(-arg); in abs_i64()
41 ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)
56 unsigned long long arg1_value = arg1_negative ? -numerator : numerator; in spl_fixpt_from_fraction()
57 unsigned long long arg2_value = arg2_negative ? -denominator : denominator; in spl_fixpt_from_fraction()
68 /* determine fractional part */ in spl_fixpt_from_fraction()
79 remainder -= arg2_value; in spl_fixpt_from_fraction()
81 } while (--i != 0); in spl_fixpt_from_fraction()
88 SPL_ASSERT(res_value <= (unsigned long long)LLONG_MAX - summand); in spl_fixpt_from_fraction()
96 res.value = -res.value; in spl_fixpt_from_fraction()
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/linux/drivers/gpu/drm/amd/display/dc/basics/
H A Dfixpt31_32.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
39 return (unsigned long long)(-arg); in abs_i64()
63 ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1)
78 unsigned long long arg1_value = arg1_negative ? -numerator : numerator; in dc_fixpt_from_fraction()
79 unsigned long long arg2_value = arg2_negative ? -denominator : denominator; in dc_fixpt_from_fraction()
90 /* determine fractional part */ in dc_fixpt_from_fraction()
101 remainder -= arg2_value; in dc_fixpt_from_fraction()
103 } while (--i != 0); in dc_fixpt_from_fraction()
110 ASSERT(res_value <= LLONG_MAX - summand); in dc_fixpt_from_fraction()
118 res.value = -res.value; in dc_fixpt_from_fraction()
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/linux/drivers/clk/
H A Dclk-fractional-divider_test.c1 // SPDX-License-Identifier: GPL-2.0
3 * Kunit tests for clk fractional divider
5 #include <linux/clk-provider.h>
8 #include "clk-fractional-divider.h"
19 unsigned long rate, parent_rate, parent_rate_before, m, n, max_n; in clk_fd_test_approximation_max_denominator() local
24 fd->mwidth = 3; in clk_fd_test_approximation_max_denominator()
25 fd->nwidth = 3; in clk_fd_test_approximation_max_denominator()
32 clk_fractional_divider_general_approximation(&fd->hw, rate, &parent_rate, &m, &n); in clk_fd_test_approximation_max_denominator()
36 KUNIT_EXPECT_EQ(test, n, max_n); in clk_fd_test_approximation_max_denominator()
48 unsigned long rate, parent_rate, parent_rate_before, m, n, max_m; in clk_fd_test_approximation_max_numerator() local
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H A Dclk-fractional-divider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Adjustable fractional divider clock implementation.
10 * rate = (m / n) * parent_rate (1)
13 * m (numerator) and n (denominator) values to be provided to satisfy
16 * Since m and n have the limitation by a range, e.g.
18 * n >= 1, n < N_width, where N_width = 2^nwidth (2)
32 * scale = floor(log2(parent_rate / rate)) - nwidth (5)
34 * and assume that the IP, that needs m and n, has also its own
37 * at the same time a much better result of m and n than simple
49 #include <linux/clk-provider.h>
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H A Dclk-si544.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
68 * struct clk_si544_muldiv - Multiplier/divider settings
70 * @fb_div_int: fractional part of feedback divider (11 bits)
73 * If ls_div_bits is non-zero, hs_div must be even
74 * @delta_m: Frequency shift for small -950..+950 ppm changes, 24 bit
87 return regmap_update_bits(data->regmap, SI544_REG_OE_STATE, in si544_enable_output()
111 err = regmap_read(data->regmap, SI544_REG_OE_STATE, &val); in si544_is_prepared()
125 err = regmap_bulk_read(data->regmap, SI544_REG_HS_DIV, reg, 2); in si544_get_muldiv()
129 settings->ls_div_bits = (reg[1] >> 4) & 0x07; in si544_get_muldiv()
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H A Dclk-plldig.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <linux/clk-provider.h>
48 * Denominator part of the fractional part of the
70 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
76 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_enable()
86 val = readl(data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
91 writel(val, data->regs + PLLDIG_REG_PLLFM); in plldig_disable()
98 return readl(data->regs + PLLDIG_REG_PLLFM) & in plldig_is_enabled()
108 val = readl(data->regs + PLLDIG_REG_PLLDV); in plldig_recalc_rate()
123 return DIV_ROUND_UP(data->vco_freq, rfdphi1); in plldig_recalc_rate()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
237 provides read-only PLLs, derived from the main crystal clock (which
296 clock. These multi-function devices have two (S2MPS14) or three
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/linux/drivers/clk/spear/
H A Dclk-frac-synth.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Fractional Synthesizer clock implementation
9 #define pr_fmt(fmt) "clk-frac-synth: " fmt
11 #include <linux/clk-provider.h>
20 * DOC: Fractional Synthesizer clock
25 * div is 17 bits:-
26 * 0-13 (fractional part)
27 * 14-16 (integer part)
28 * div is (16-14 bits).(13-0 bits) (in binary)
45 struct frac_rate_tbl *rtbl = frac->rtbl; in frac_calc_rate()
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/linux/drivers/clk/renesas/
H A Drcar-gen4-cpg.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen4 Clock Pulse Generator
7 * Based on rcar-gen3-cpg.c
9 * Copyright (C) 2015-2018 Glider bvba
15 #include <linux/clk-provider.h>
23 #include "renesas-cpg-mssr.h"
24 #include "rcar-gen4-cpg.h"
25 #include "rcar-cpg-lib.h"
33 #define CPG_PLLECR_PLLST(n) BIT(8 + ((n) < 3 ? (n) - 1 : \ argument
34 (n) > 3 ? (n) + 1 : n)) /* PLLn Circuit Status */
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/linux/drivers/clk/sunxi-ng/
H A Dccu_frac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 #include <linux/clk-provider.h>
16 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_is_enabled()
19 return !(readl(common->base + common->reg) & cf->enable); in ccu_frac_helper_is_enabled()
29 if (!(common->features & CCU_FEATURE_FRACTIONAL)) in ccu_frac_helper_enable()
32 spin_lock_irqsave(common->lock, flags); in ccu_frac_helper_enable()
33 reg = readl(common->base + common->reg); in ccu_frac_helper_enable()
34 writel(reg & ~cf->enable, common->base + common->reg); in ccu_frac_helper_enable()
35 spin_unlock_irqrestore(common->lock, flags); in ccu_frac_helper_enable()
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/linux/drivers/clk/zynqmp/
H A Ddivider.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Xilinx
11 #include <linux/clk-provider.h>
13 #include "clk-zynqmp.h"
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
22 * parent - fixed parent. No clk_set_parent support
28 #define CLK_FRAC BIT(13) /* has a fractional parent */
29 #define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */
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/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <linux/clk-provider.h>
64 /* The lookup table contains values for which the fractional divder is used */
286 /* PHY_REG(1-7) pix clk specific */
332 u32 pclk = cfg->pixclk; in fsl_samsung_hdmi_phy_configure_pll_lock_det()
345 return -EINVAL; in fsl_samsung_hdmi_phy_configure_pll_lock_det()
347 writeb(FIELD_PREP(REG12_CK_DIV_MASK, div), phy->regs + PHY_REG(12)); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
365 phy->regs + PHY_REG(13)); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
369 phy->regs + PHY_REG(14)); in fsl_samsung_hdmi_phy_configure_pll_lock_det()
383 * Figure 13-78 of the reference manual states the PLL should be TMDS x 5 in fsl_samsung_hdmi_phy_find_pms()
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/linux/sound/soc/tegra/
H A Dtegra186_asrc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 // tegra186_asrc.c - Tegra186 ASRC driver
73 regmap_write(asrc->regmap, in tegra186_asrc_lock_stream()
83 regcache_cache_only(asrc->regmap, true); in tegra186_asrc_runtime_suspend()
84 regcache_mark_dirty(asrc->regmap); in tegra186_asrc_runtime_suspend()
94 regcache_cache_only(asrc->regmap, false); in tegra186_asrc_runtime_resume()
101 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_SCRATCH_ADDR, in tegra186_asrc_runtime_resume()
103 regmap_write(asrc->regmap, TEGRA186_ASRC_GLOBAL_ENB, in tegra186_asrc_runtime_resume()
106 regcache_sync(asrc->regmap); in tegra186_asrc_runtime_resume()
109 if (asrc->lane[id].ratio_source != in tegra186_asrc_runtime_resume()
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/linux/drivers/hwmon/
H A Demc2103.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * emc2103.c - Support for SMSC EMC2103
13 #include <linux/hwmon-sysfs.h>
39 * 2103-2 and 2103-4's 3rd temperature sensor can be connected to two diodes
40 * in anti-parallel mode, and in this configuration both can be read
43 * it. Default is to leave the device in the state it's already in (-1).
46 static int apd = -1;
48 MODULE_PARM_DESC(apd, "Set to zero to disable anti-parallel diode mode");
52 u8 fraction; /* 0-7 multiples of 0.125 */
64 s8 temp_min[4]; /* no fractional part */
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/linux/drivers/rtc/
H A Drtc-zynqmp.c1 // SPDX-License-Identifier: GPL-2.0
47 #define RTC_MIN_OFFSET -32768000
71 writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR); in xlnx_rtc_set_time()
81 writel(RTC_INT_SEC, xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_set_time()
92 status = readl(xrtcdev->reg_base + RTC_INT_STS); in xlnx_rtc_read_time()
99 read_time = readl(xrtcdev->reg_base + RTC_CUR_TM); in xlnx_rtc_read_time()
105 * Since we add +1 sec while writing, we need to -1 sec while in xlnx_rtc_read_time()
108 read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1; in xlnx_rtc_read_time()
119 rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time); in xlnx_rtc_read_alarm()
120 alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM; in xlnx_rtc_read_alarm()
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/linux/drivers/clk/at91/
H A Dsam9x7.c1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/clk-provider.h>
15 #include <dt-bindings/clock/at91.h>
23 * enum pll_ids - PLL clocks identifiers
41 * enum pll_type - PLL type identifiers
42 * @PLL_TYPE_FRAC: fractional PLL identifier
62 /* Fractional PLL core output range. */
83 /* Fractional PLL output range. */
141 /* Layout for fractional PLL ID PLLA. */
150 /* Layout for fractional PLLs. */
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/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_abm.c2 * Copyright 2012-16 Advanced Micro Devices, Inc.
41 (abm_dce->regs->reg)
45 abm_dce->abm_shift->field_name, abm_dce->abm_mask->field_name
48 abm->ctx->logger
50 abm_dce->base.ctx
63 if (abm->dmcu_is_running == false) in dce_abm_set_pipe()
100 // Take MSB of fractional part since backlight is not max in dmcu_set_backlight_level()
103 dce_abm_set_pipe(&abm_dce->base, controller_id, panel_id); in dmcu_set_backlight_level()
183 * 1 bit integer and 16 bit fractional in dce_abm_get_current_backlight()
194 * 1 bit integer and 16 bit fractional in dce_abm_get_target_backlight()
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_pll.c33 * amdgpu_pll_reduce_ratio - fractional number reduction
70 * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation
91 if (adev->family == AMDGPU_FAMILY_SI) in amdgpu_pll_get_fb_ref_div()
108 * amdgpu_pll_compute - compute PLL paramaters
115 * @frac_fb_div_p: fractional part of the feedback divider
131 unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? in amdgpu_pll_compute()
141 fb_div_min = pll->min_feedback_div; in amdgpu_pll_compute()
142 fb_div_max = pll->max_feedback_div; in amdgpu_pll_compute()
144 if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { in amdgpu_pll_compute()
150 if (pll->flags & AMDGPU_PLL_USE_REF_DIV) in amdgpu_pll_compute()
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/linux/sound/soc/codecs/
H A Dadau-utils.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2011-2016 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
13 #include "adau-utils.h"
18 unsigned int r, n, m, i, j; in adau_calc_pll_cfg() local
23 n = 0; in adau_calc_pll_cfg()
33 n = i / j; in adau_calc_pll_cfg()
35 div--; in adau_calc_pll_cfg()
38 n = 0; in adau_calc_pll_cfg()
42 if (n > 0xffff || m > 0xffff || div > 3 || r > 8 || r < 2) in adau_calc_pll_cfg()
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/linux/Documentation/ABI/testing/
H A Dsysfs-bus-iio-frequency-adf43503 Contact: linux-iio@vger.kernel.org
7 the fractional-N PLL. It is assumed that the algorithm
13 Contact: linux-iio@vger.kernel.org
/linux/drivers/clk/ti/
H A Dfapll.c1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass()
83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass()
91 u32 v = readl_relaxed(fd->base); in ti_fapll_set_bypass()
93 if (fd->bypass_bit_inverted) in ti_fapll_set_bypass()
97 writel_relaxed(v, fd->base); in ti_fapll_set_bypass()
102 u32 v = readl_relaxed(fd->base); in ti_fapll_clear_bypass()
104 if (fd->bypass_bit_inverted) in ti_fapll_clear_bypass()
108 writel_relaxed(v, fd->base); in ti_fapll_clear_bypass()
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/linux/arch/powerpc/platforms/512x/
H A Dclock-commonclk.c1 // SPDX-License-Identifier: GPL-2.0-or-later
12 #include <linux/clk-provider.h>
21 #include <dt-bindings/clock/mpc512x-clock.h>
47 /* intermediates in div+gate combos or fractional dividers */
89 * interpretation, no CFM, different fourth PSC/CAN mux0 input -- yet
292 val &= (1 << len) - 1; in get_bit_field()
305 spmf = get_bit_field(&clkregs->spmr, 24, 4); in get_spmf_mult()
313 * divide ratio is fractional
326 divcode = get_bit_field(&clkregs->scfr2, 26, 6); in get_sys_div_x2()
334 * multiplier ratio is fractional
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/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv4420.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nuno Sá <nuno.sa@analog.com>
14 mixer with an integrated fractional-N synthesizer, ideally suited
20 - adi,admv4420
25 spi-max-frequency:
28 adi,lo-freq-khz:
32 adi,ref-ext-single-ended-en:
37 - compatible
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/linux/arch/arm/include/asm/
H A Ddelay.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1995-2004 Russell King
5 * Delay routines, using a pre-computed "loops_per_second" value.
24 * fractional number. To make this usable with integer math, we
58 #define __delay(n) arm_delay_ops.delay(n) argument
79 #define __udelay(n) arm_delay_ops.udelay(n) argument
80 #define __const_udelay(n) arm_delay_ops.const_udelay(n) argument
82 #define udelay(n) \ argument
83 (__builtin_constant_p(n) ? \
84 ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() : \
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/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
54 #define MAX_SMNCLK_DPM_LEVEL (NUM_SMNCLK_DPM_LEVELS - 1)
55 #define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
56 #define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
57 #define MAX_DCLK_DPM_LEVEL (NUM_DCLK_DPM_LEVELS - 1)
58 #define MAX_VCLK_DPM_LEVEL (NUM_VCLK_DPM_LEVELS - 1)
59 #define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
60 #define MAX_DISPCLK_DPM_LEVEL (NUM_DISPCLK_DPM_LEVELS - 1)
61 #define MAX_PIXCLK_DPM_LEVEL (NUM_PIXCLK_DPM_LEVELS - 1)
62 #define MAX_PHYCLK_DPM_LEVEL (NUM_PHYCLK_DPM_LEVELS - 1)
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