1d38ceaf9SAlex Deucher /* 2d38ceaf9SAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 3d38ceaf9SAlex Deucher * 4d38ceaf9SAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 5d38ceaf9SAlex Deucher * copy of this software and associated documentation files (the "Software"), 6d38ceaf9SAlex Deucher * to deal in the Software without restriction, including without limitation 7d38ceaf9SAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8d38ceaf9SAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 9d38ceaf9SAlex Deucher * Software is furnished to do so, subject to the following conditions: 10d38ceaf9SAlex Deucher * 11d38ceaf9SAlex Deucher * The above copyright notice and this permission notice shall be included in 12d38ceaf9SAlex Deucher * all copies or substantial portions of the Software. 13d38ceaf9SAlex Deucher * 14d38ceaf9SAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15d38ceaf9SAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16d38ceaf9SAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17d38ceaf9SAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18d38ceaf9SAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19d38ceaf9SAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20d38ceaf9SAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 21d38ceaf9SAlex Deucher * 22d38ceaf9SAlex Deucher */ 23fdf2f6c5SSam Ravnborg 24d38ceaf9SAlex Deucher #include <drm/amdgpu_drm.h> 25d38ceaf9SAlex Deucher #include "amdgpu.h" 26d38ceaf9SAlex Deucher #include "atom.h" 27d38ceaf9SAlex Deucher #include "atombios_encoders.h" 289ca91fddSBaoyou Xie #include "amdgpu_pll.h" 29d38ceaf9SAlex Deucher #include <asm/div64.h> 30d38ceaf9SAlex Deucher #include <linux/gcd.h> 31d38ceaf9SAlex Deucher 32d38ceaf9SAlex Deucher /** 33d38ceaf9SAlex Deucher * amdgpu_pll_reduce_ratio - fractional number reduction 34d38ceaf9SAlex Deucher * 35d38ceaf9SAlex Deucher * @nom: nominator 36d38ceaf9SAlex Deucher * @den: denominator 37d38ceaf9SAlex Deucher * @nom_min: minimum value for nominator 38d38ceaf9SAlex Deucher * @den_min: minimum value for denominator 39d38ceaf9SAlex Deucher * 40d38ceaf9SAlex Deucher * Find the greatest common divisor and apply it on both nominator and 41d38ceaf9SAlex Deucher * denominator, but make nominator and denominator are at least as large 42d38ceaf9SAlex Deucher * as their minimum values. 43d38ceaf9SAlex Deucher */ 44d38ceaf9SAlex Deucher static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den, 45d38ceaf9SAlex Deucher unsigned nom_min, unsigned den_min) 46d38ceaf9SAlex Deucher { 47d38ceaf9SAlex Deucher unsigned tmp; 48d38ceaf9SAlex Deucher 49d38ceaf9SAlex Deucher /* reduce the numbers to a simpler ratio */ 50d38ceaf9SAlex Deucher tmp = gcd(*nom, *den); 51d38ceaf9SAlex Deucher *nom /= tmp; 52d38ceaf9SAlex Deucher *den /= tmp; 53d38ceaf9SAlex Deucher 54d38ceaf9SAlex Deucher /* make sure nominator is large enough */ 55d38ceaf9SAlex Deucher if (*nom < nom_min) { 56d38ceaf9SAlex Deucher tmp = DIV_ROUND_UP(nom_min, *nom); 57d38ceaf9SAlex Deucher *nom *= tmp; 58d38ceaf9SAlex Deucher *den *= tmp; 59d38ceaf9SAlex Deucher } 60d38ceaf9SAlex Deucher 61d38ceaf9SAlex Deucher /* make sure the denominator is large enough */ 62d38ceaf9SAlex Deucher if (*den < den_min) { 63d38ceaf9SAlex Deucher tmp = DIV_ROUND_UP(den_min, *den); 64d38ceaf9SAlex Deucher *nom *= tmp; 65d38ceaf9SAlex Deucher *den *= tmp; 66d38ceaf9SAlex Deucher } 67d38ceaf9SAlex Deucher } 68d38ceaf9SAlex Deucher 69d38ceaf9SAlex Deucher /** 70d38ceaf9SAlex Deucher * amdgpu_pll_get_fb_ref_div - feedback and ref divider calculation 71d38ceaf9SAlex Deucher * 72bbe04decSIsabella Basso * @adev: amdgpu_device pointer 73d38ceaf9SAlex Deucher * @nom: nominator 74d38ceaf9SAlex Deucher * @den: denominator 75d38ceaf9SAlex Deucher * @post_div: post divider 76d38ceaf9SAlex Deucher * @fb_div_max: feedback divider maximum 77d38ceaf9SAlex Deucher * @ref_div_max: reference divider maximum 78d38ceaf9SAlex Deucher * @fb_div: resulting feedback divider 79d38ceaf9SAlex Deucher * @ref_div: resulting reference divider 80d38ceaf9SAlex Deucher * 81d38ceaf9SAlex Deucher * Calculate feedback and reference divider for a given post divider. Makes 82d38ceaf9SAlex Deucher * sure we stay within the limits. 83d38ceaf9SAlex Deucher */ 847301757eSShashank Sharma static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom, 857301757eSShashank Sharma unsigned int den, unsigned int post_div, 867301757eSShashank Sharma unsigned int fb_div_max, unsigned int ref_div_max, 877301757eSShashank Sharma unsigned int *fb_div, unsigned int *ref_div) 88d38ceaf9SAlex Deucher { 897301757eSShashank Sharma 90d38ceaf9SAlex Deucher /* limit reference * post divider to a maximum */ 917301757eSShashank Sharma if (adev->family == AMDGPU_FAMILY_SI) 927301757eSShashank Sharma ref_div_max = min(100 / post_div, ref_div_max); 937301757eSShashank Sharma else 94d38ceaf9SAlex Deucher ref_div_max = min(128 / post_div, ref_div_max); 95d38ceaf9SAlex Deucher 96d38ceaf9SAlex Deucher /* get matching reference and feedback divider */ 97*6fbbb660SLi Zetao *ref_div = clamp(DIV_ROUND_CLOSEST(den, post_div), 1u, ref_div_max); 98d38ceaf9SAlex Deucher *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); 99d38ceaf9SAlex Deucher 100d38ceaf9SAlex Deucher /* limit fb divider to its maximum */ 101d38ceaf9SAlex Deucher if (*fb_div > fb_div_max) { 102d38ceaf9SAlex Deucher *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); 103d38ceaf9SAlex Deucher *fb_div = fb_div_max; 104d38ceaf9SAlex Deucher } 105d38ceaf9SAlex Deucher } 106d38ceaf9SAlex Deucher 107d38ceaf9SAlex Deucher /** 108d38ceaf9SAlex Deucher * amdgpu_pll_compute - compute PLL paramaters 109d38ceaf9SAlex Deucher * 110bbe04decSIsabella Basso * @adev: amdgpu_device pointer 111d38ceaf9SAlex Deucher * @pll: information about the PLL 112211880a6SLee Jones * @freq: requested frequency 113d38ceaf9SAlex Deucher * @dot_clock_p: resulting pixel clock 114211880a6SLee Jones * @fb_div_p: resulting feedback divider 115211880a6SLee Jones * @frac_fb_div_p: fractional part of the feedback divider 116211880a6SLee Jones * @ref_div_p: resulting reference divider 117211880a6SLee Jones * @post_div_p: resulting reference divider 118d38ceaf9SAlex Deucher * 119d38ceaf9SAlex Deucher * Try to calculate the PLL parameters to generate the given frequency: 120d38ceaf9SAlex Deucher * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div) 121d38ceaf9SAlex Deucher */ 1227301757eSShashank Sharma void amdgpu_pll_compute(struct amdgpu_device *adev, 1237301757eSShashank Sharma struct amdgpu_pll *pll, 124d38ceaf9SAlex Deucher u32 freq, 125d38ceaf9SAlex Deucher u32 *dot_clock_p, 126d38ceaf9SAlex Deucher u32 *fb_div_p, 127d38ceaf9SAlex Deucher u32 *frac_fb_div_p, 128d38ceaf9SAlex Deucher u32 *ref_div_p, 129d38ceaf9SAlex Deucher u32 *post_div_p) 130d38ceaf9SAlex Deucher { 131d38ceaf9SAlex Deucher unsigned target_clock = pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV ? 132d38ceaf9SAlex Deucher freq : freq / 10; 133d38ceaf9SAlex Deucher 134d38ceaf9SAlex Deucher unsigned fb_div_min, fb_div_max, fb_div; 135d38ceaf9SAlex Deucher unsigned post_div_min, post_div_max, post_div; 136d38ceaf9SAlex Deucher unsigned ref_div_min, ref_div_max, ref_div; 137d38ceaf9SAlex Deucher unsigned post_div_best, diff_best; 138d38ceaf9SAlex Deucher unsigned nom, den; 139d38ceaf9SAlex Deucher 140d38ceaf9SAlex Deucher /* determine allowed feedback divider range */ 141d38ceaf9SAlex Deucher fb_div_min = pll->min_feedback_div; 142d38ceaf9SAlex Deucher fb_div_max = pll->max_feedback_div; 143d38ceaf9SAlex Deucher 144d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { 145d38ceaf9SAlex Deucher fb_div_min *= 10; 146d38ceaf9SAlex Deucher fb_div_max *= 10; 147d38ceaf9SAlex Deucher } 148d38ceaf9SAlex Deucher 149d38ceaf9SAlex Deucher /* determine allowed ref divider range */ 150d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_REF_DIV) 151d38ceaf9SAlex Deucher ref_div_min = pll->reference_div; 152d38ceaf9SAlex Deucher else 153d38ceaf9SAlex Deucher ref_div_min = pll->min_ref_div; 154d38ceaf9SAlex Deucher 155d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && 156d38ceaf9SAlex Deucher pll->flags & AMDGPU_PLL_USE_REF_DIV) 157d38ceaf9SAlex Deucher ref_div_max = pll->reference_div; 158d38ceaf9SAlex Deucher else 159d38ceaf9SAlex Deucher ref_div_max = pll->max_ref_div; 160d38ceaf9SAlex Deucher 161d38ceaf9SAlex Deucher /* determine allowed post divider range */ 162d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_POST_DIV) { 163d38ceaf9SAlex Deucher post_div_min = pll->post_div; 164d38ceaf9SAlex Deucher post_div_max = pll->post_div; 165d38ceaf9SAlex Deucher } else { 166d38ceaf9SAlex Deucher unsigned vco_min, vco_max; 167d38ceaf9SAlex Deucher 168d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_IS_LCD) { 169d38ceaf9SAlex Deucher vco_min = pll->lcd_pll_out_min; 170d38ceaf9SAlex Deucher vco_max = pll->lcd_pll_out_max; 171d38ceaf9SAlex Deucher } else { 172d38ceaf9SAlex Deucher vco_min = pll->pll_out_min; 173d38ceaf9SAlex Deucher vco_max = pll->pll_out_max; 174d38ceaf9SAlex Deucher } 175d38ceaf9SAlex Deucher 176d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { 177d38ceaf9SAlex Deucher vco_min *= 10; 178d38ceaf9SAlex Deucher vco_max *= 10; 179d38ceaf9SAlex Deucher } 180d38ceaf9SAlex Deucher 181d38ceaf9SAlex Deucher post_div_min = vco_min / target_clock; 182d38ceaf9SAlex Deucher if ((target_clock * post_div_min) < vco_min) 183d38ceaf9SAlex Deucher ++post_div_min; 184d38ceaf9SAlex Deucher if (post_div_min < pll->min_post_div) 185d38ceaf9SAlex Deucher post_div_min = pll->min_post_div; 186d38ceaf9SAlex Deucher 187d38ceaf9SAlex Deucher post_div_max = vco_max / target_clock; 188d38ceaf9SAlex Deucher if ((target_clock * post_div_max) > vco_max) 189d38ceaf9SAlex Deucher --post_div_max; 190d38ceaf9SAlex Deucher if (post_div_max > pll->max_post_div) 191d38ceaf9SAlex Deucher post_div_max = pll->max_post_div; 192d38ceaf9SAlex Deucher } 193d38ceaf9SAlex Deucher 194d38ceaf9SAlex Deucher /* represent the searched ratio as fractional number */ 195d38ceaf9SAlex Deucher nom = target_clock; 196d38ceaf9SAlex Deucher den = pll->reference_freq; 197d38ceaf9SAlex Deucher 198d38ceaf9SAlex Deucher /* reduce the numbers to a simpler ratio */ 199d38ceaf9SAlex Deucher amdgpu_pll_reduce_ratio(&nom, &den, fb_div_min, post_div_min); 200d38ceaf9SAlex Deucher 201d38ceaf9SAlex Deucher /* now search for a post divider */ 202d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP) 203d38ceaf9SAlex Deucher post_div_best = post_div_min; 204d38ceaf9SAlex Deucher else 205d38ceaf9SAlex Deucher post_div_best = post_div_max; 206d38ceaf9SAlex Deucher diff_best = ~0; 207d38ceaf9SAlex Deucher 208d38ceaf9SAlex Deucher for (post_div = post_div_min; post_div <= post_div_max; ++post_div) { 209d38ceaf9SAlex Deucher unsigned diff; 2107301757eSShashank Sharma amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, 211d38ceaf9SAlex Deucher ref_div_max, &fb_div, &ref_div); 212d38ceaf9SAlex Deucher diff = abs(target_clock - (pll->reference_freq * fb_div) / 213d38ceaf9SAlex Deucher (ref_div * post_div)); 214d38ceaf9SAlex Deucher 215d38ceaf9SAlex Deucher if (diff < diff_best || (diff == diff_best && 216d38ceaf9SAlex Deucher !(pll->flags & AMDGPU_PLL_PREFER_MINM_OVER_MAXP))) { 217d38ceaf9SAlex Deucher 218d38ceaf9SAlex Deucher post_div_best = post_div; 219d38ceaf9SAlex Deucher diff_best = diff; 220d38ceaf9SAlex Deucher } 221d38ceaf9SAlex Deucher } 222d38ceaf9SAlex Deucher post_div = post_div_best; 223d38ceaf9SAlex Deucher 224d38ceaf9SAlex Deucher /* get the feedback and reference divider for the optimal value */ 2257301757eSShashank Sharma amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, ref_div_max, 226d38ceaf9SAlex Deucher &fb_div, &ref_div); 227d38ceaf9SAlex Deucher 228d38ceaf9SAlex Deucher /* reduce the numbers to a simpler ratio once more */ 229d38ceaf9SAlex Deucher /* this also makes sure that the reference divider is large enough */ 230d38ceaf9SAlex Deucher amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); 231d38ceaf9SAlex Deucher 232d38ceaf9SAlex Deucher /* avoid high jitter with small fractional dividers */ 233d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV && (fb_div % 10)) { 234d38ceaf9SAlex Deucher fb_div_min = max(fb_div_min, (9 - (fb_div % 10)) * 20 + 60); 235d38ceaf9SAlex Deucher if (fb_div < fb_div_min) { 236d38ceaf9SAlex Deucher unsigned tmp = DIV_ROUND_UP(fb_div_min, fb_div); 237d38ceaf9SAlex Deucher fb_div *= tmp; 238d38ceaf9SAlex Deucher ref_div *= tmp; 239d38ceaf9SAlex Deucher } 240d38ceaf9SAlex Deucher } 241d38ceaf9SAlex Deucher 242d38ceaf9SAlex Deucher /* and finally save the result */ 243d38ceaf9SAlex Deucher if (pll->flags & AMDGPU_PLL_USE_FRAC_FB_DIV) { 244d38ceaf9SAlex Deucher *fb_div_p = fb_div / 10; 245d38ceaf9SAlex Deucher *frac_fb_div_p = fb_div % 10; 246d38ceaf9SAlex Deucher } else { 247d38ceaf9SAlex Deucher *fb_div_p = fb_div; 248d38ceaf9SAlex Deucher *frac_fb_div_p = 0; 249d38ceaf9SAlex Deucher } 250d38ceaf9SAlex Deucher 251d38ceaf9SAlex Deucher *dot_clock_p = ((pll->reference_freq * *fb_div_p * 10) + 252d38ceaf9SAlex Deucher (pll->reference_freq * *frac_fb_div_p)) / 253d38ceaf9SAlex Deucher (ref_div * post_div * 10); 254d38ceaf9SAlex Deucher *ref_div_p = ref_div; 255d38ceaf9SAlex Deucher *post_div_p = post_div; 256d38ceaf9SAlex Deucher 257d38ceaf9SAlex Deucher DRM_DEBUG_KMS("%d - %d, pll dividers - fb: %d.%d ref: %d, post %d\n", 258d38ceaf9SAlex Deucher freq, *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, 259d38ceaf9SAlex Deucher ref_div, post_div); 260d38ceaf9SAlex Deucher } 261d38ceaf9SAlex Deucher 262d38ceaf9SAlex Deucher /** 263d38ceaf9SAlex Deucher * amdgpu_pll_get_use_mask - look up a mask of which pplls are in use 264d38ceaf9SAlex Deucher * 265d38ceaf9SAlex Deucher * @crtc: drm crtc 266d38ceaf9SAlex Deucher * 267d38ceaf9SAlex Deucher * Returns the mask of which PPLLs (Pixel PLLs) are in use. 268d38ceaf9SAlex Deucher */ 269d38ceaf9SAlex Deucher u32 amdgpu_pll_get_use_mask(struct drm_crtc *crtc) 270d38ceaf9SAlex Deucher { 271d38ceaf9SAlex Deucher struct drm_device *dev = crtc->dev; 272d38ceaf9SAlex Deucher struct drm_crtc *test_crtc; 273d38ceaf9SAlex Deucher struct amdgpu_crtc *test_amdgpu_crtc; 274d38ceaf9SAlex Deucher u32 pll_in_use = 0; 275d38ceaf9SAlex Deucher 276d38ceaf9SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 277d38ceaf9SAlex Deucher if (crtc == test_crtc) 278d38ceaf9SAlex Deucher continue; 279d38ceaf9SAlex Deucher 280d38ceaf9SAlex Deucher test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); 281d38ceaf9SAlex Deucher if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) 282d38ceaf9SAlex Deucher pll_in_use |= (1 << test_amdgpu_crtc->pll_id); 283d38ceaf9SAlex Deucher } 284d38ceaf9SAlex Deucher return pll_in_use; 285d38ceaf9SAlex Deucher } 286d38ceaf9SAlex Deucher 287d38ceaf9SAlex Deucher /** 288d38ceaf9SAlex Deucher * amdgpu_pll_get_shared_dp_ppll - return the PPLL used by another crtc for DP 289d38ceaf9SAlex Deucher * 290d38ceaf9SAlex Deucher * @crtc: drm crtc 291d38ceaf9SAlex Deucher * 292d38ceaf9SAlex Deucher * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is 293d38ceaf9SAlex Deucher * also in DP mode. For DP, a single PPLL can be used for all DP 294d38ceaf9SAlex Deucher * crtcs/encoders. 295d38ceaf9SAlex Deucher */ 296d38ceaf9SAlex Deucher int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc) 297d38ceaf9SAlex Deucher { 298d38ceaf9SAlex Deucher struct drm_device *dev = crtc->dev; 299d38ceaf9SAlex Deucher struct drm_crtc *test_crtc; 300d38ceaf9SAlex Deucher struct amdgpu_crtc *test_amdgpu_crtc; 301d38ceaf9SAlex Deucher 302d38ceaf9SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 303d38ceaf9SAlex Deucher if (crtc == test_crtc) 304d38ceaf9SAlex Deucher continue; 305d38ceaf9SAlex Deucher test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); 306d38ceaf9SAlex Deucher if (test_amdgpu_crtc->encoder && 307d38ceaf9SAlex Deucher ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) { 308d38ceaf9SAlex Deucher /* for DP use the same PLL for all */ 309d38ceaf9SAlex Deucher if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) 310d38ceaf9SAlex Deucher return test_amdgpu_crtc->pll_id; 311d38ceaf9SAlex Deucher } 312d38ceaf9SAlex Deucher } 313d38ceaf9SAlex Deucher return ATOM_PPLL_INVALID; 314d38ceaf9SAlex Deucher } 315d38ceaf9SAlex Deucher 316d38ceaf9SAlex Deucher /** 317d38ceaf9SAlex Deucher * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc 318d38ceaf9SAlex Deucher * 319d38ceaf9SAlex Deucher * @crtc: drm crtc 320d38ceaf9SAlex Deucher * 321d38ceaf9SAlex Deucher * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can 322d38ceaf9SAlex Deucher * be shared (i.e., same clock). 323d38ceaf9SAlex Deucher */ 324d38ceaf9SAlex Deucher int amdgpu_pll_get_shared_nondp_ppll(struct drm_crtc *crtc) 325d38ceaf9SAlex Deucher { 326d38ceaf9SAlex Deucher struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); 327d38ceaf9SAlex Deucher struct drm_device *dev = crtc->dev; 328d38ceaf9SAlex Deucher struct drm_crtc *test_crtc; 329d38ceaf9SAlex Deucher struct amdgpu_crtc *test_amdgpu_crtc; 330d38ceaf9SAlex Deucher u32 adjusted_clock, test_adjusted_clock; 331d38ceaf9SAlex Deucher 332d38ceaf9SAlex Deucher adjusted_clock = amdgpu_crtc->adjusted_clock; 333d38ceaf9SAlex Deucher 334d38ceaf9SAlex Deucher if (adjusted_clock == 0) 335d38ceaf9SAlex Deucher return ATOM_PPLL_INVALID; 336d38ceaf9SAlex Deucher 337d38ceaf9SAlex Deucher list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) { 338d38ceaf9SAlex Deucher if (crtc == test_crtc) 339d38ceaf9SAlex Deucher continue; 340d38ceaf9SAlex Deucher test_amdgpu_crtc = to_amdgpu_crtc(test_crtc); 341d38ceaf9SAlex Deucher if (test_amdgpu_crtc->encoder && 342d38ceaf9SAlex Deucher !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(test_amdgpu_crtc->encoder))) { 343d38ceaf9SAlex Deucher /* check if we are already driving this connector with another crtc */ 344d38ceaf9SAlex Deucher if (test_amdgpu_crtc->connector == amdgpu_crtc->connector) { 345d38ceaf9SAlex Deucher /* if we are, return that pll */ 346d38ceaf9SAlex Deucher if (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID) 347d38ceaf9SAlex Deucher return test_amdgpu_crtc->pll_id; 348d38ceaf9SAlex Deucher } 349d38ceaf9SAlex Deucher /* for non-DP check the clock */ 350d38ceaf9SAlex Deucher test_adjusted_clock = test_amdgpu_crtc->adjusted_clock; 351d38ceaf9SAlex Deucher if ((crtc->mode.clock == test_crtc->mode.clock) && 352d38ceaf9SAlex Deucher (adjusted_clock == test_adjusted_clock) && 353d38ceaf9SAlex Deucher (amdgpu_crtc->ss_enabled == test_amdgpu_crtc->ss_enabled) && 354d38ceaf9SAlex Deucher (test_amdgpu_crtc->pll_id != ATOM_PPLL_INVALID)) 355d38ceaf9SAlex Deucher return test_amdgpu_crtc->pll_id; 356d38ceaf9SAlex Deucher } 357d38ceaf9SAlex Deucher } 358d38ceaf9SAlex Deucher return ATOM_PPLL_INVALID; 359d38ceaf9SAlex Deucher } 360