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/freebsd/sys/contrib/device-tree/Bindings/fpga/
H A Dfpga-region.txt1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Devic
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H A Dxilinx-pr-decoupler.txt4 decouplers / fpga bridges.
11 Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
15 and AXI4-Lite interfaces on a Reconfigurable Partition when it is
19 The Driver supports only MMIO handling. A PR region can have multiple
24 - compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
25 "xlnx,pr-decoupler" or
26 "xlnx,dfx-axi-shutdown-manager-1.00" followed by
27 "xlnx,dfx-axi-shutdown-manager"
28 - regs : base address and size for decoupler module
29 - clocks : input clock to IP
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H A Dxlnx,zynqmp-pcap-fpga.txt1 Devicetree bindings for Zynq Ultrascale MPSoC FPGA Manager.
6 - compatible: should contain "xlnx,zynqmp-pcap-fpga"
8 Example for full FPGA configuration:
10 fpga-region0 {
11 compatible = "fpga-region";
12 fpga-mgr = <&zynqmp_pcap>;
13 #address-cells = <0x1>;
14 #size-cells = <0x1>;
18 zynqmp_firmware: zynqmp-firmware {
19 compatible = "xlnx,zynqmp-firmware";
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H A Dlattice-machxo2-spi.txt1 Lattice MachXO2 Slave SPI FPGA Manager
9 - compatible: should contain "lattice,machxo2-slave-spi"
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
17 #address-cells = <0x1>;
18 #size-cells = <0x1>;
24 fpga_mgr_spi: fpga-mgr@0 {
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H A Dxilinx-slave-serial.txt1 Xilinx Slave Serial SPI FPGA Manager
3 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
9 - https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
10 - https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
11 - https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
14 - compatible: should contain "xlnx,fpga-slave-serial"
15 - reg: spi chip select of the FPGA
16 - prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
17 - done-gpios: config status pin (referred to as DONE in the manual)
20 - init-b-gpios: initialization status and configuration error pin
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H A Dxlnx,pr-decoupler.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xln
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/freebsd/sys/contrib/device-tree/Bindings/firmware/
H A Dintel,stratix10-svc.txt3 Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard
4 processor system (HPS) and Secure Device Manager (SDM). When the FPGA is
7 configuration data from that location and perform the FPGA configuration.
17 the services for FPGA configuration, QSPI, Crypto and warm reset. Service layer
22 -------------------
26 - compatible: "intel,stratix10-svc" or "intel,agilex-svc"
27 - method: smc or hvc
28 smc - Secure Monitor Call
29 hvc - Hypervisor Call
30 - memory-region:
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/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dgpio-ts4900.txt1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
12 of memory mapped region.
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
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H A Dgpio-ts4800.txt1 * TS-4800 FPGA's GPIO controller bindings
4 - compatible: Must be "technologic,ts4800-gpio".
5 - #gpio-cells: Should be two. The first cell is the pin number.
6 - reg: Physical base address of the controller and length
7 of memory mapped region.
10 - ngpios: See "gpio.txt"
15 compatible = "technologic,ts4800-gpio";
18 gpio-controller;
19 #gpio-cells = <2>;
/freebsd/sys/contrib/device-tree/Bindings/input/touchscreen/
H A Dts4800-ts.txt1 * TS-4800 Touchscreen bindings
4 - compatible: must be "technologic,ts4800-ts"
5 - reg: physical base address of the controller and length of memory mapped
6 region.
7 - syscon: phandle / integers array that points to the syscon node which
8 describes the FPGA's syscon registers.
9 - phandle to FPGA's syscon
10 - offset to the touchscreen register
11 - offset to the touchscreen enable bit
/freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/
H A Dtechnologic,ts4800.txt1 TS-4800 FPGA interrupt controller
3 TS-4800 FPGA has an internal interrupt controller. When one of the
8 - compatible: should be "technologic,ts4800-irqc"
9 - interrupt-controller: identifies the node as an interrupt controller
10 - reg: physical base address of the controller and length of memory mapped
11 region
12 - #interrupt-cells: specifies the number of cells needed to encode an interrupt
14 - interrupts: specifies the interrupt line in the interrupt-parent controller
/freebsd/sys/contrib/device-tree/src/arm/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controlle
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/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-binding
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/freebsd/sys/contrib/device-tree/src/arm/aspeed/
H A Daspeed-bmc-amd-ethanolx.dts1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
26 compatible = "shared-dma-pool";
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H A Daspeed-bmc-tyan-s8036.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "aspeed-g5.dtsi"
5 #include <dt-bindings/gpio/aspeed-gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 compatible = "tyan,s8036-bmc", "aspeed,ast2500";
13 stdout-path = &uart5;
22 reserved-memory {
23 #address-cells = <1>;
24 #size-cells = <1>;
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/freebsd/sys/contrib/device-tree/Bindings/display/
H A Dxylon,logicvc-display.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
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/freebsd/sys/contrib/device-tree/src/arm64/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controlle
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/gpio-keys.h>
14 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 /delete-nod
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/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
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H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cell
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/freebsd/sys/contrib/device-tree/src/arm/arm/
H A Dvexpress-v2m.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
14 * RS1 variant (vexpress-v2m-rs1.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m-rs1.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
24 compatible = "simple-bus";
25 #address-cells = <1>;
26 #size-cells = <1>;
30 #interrupt-cells = <1>;
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H A Dvexpress-v2m-rs1.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 v2m_fixed_3v3: fixed-regulator-0 {
24 compatible = "regulator-fixed";
25 regulator-name = "3V3";
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/freebsd/sys/contrib/device-tree/src/arm64/arm/
H A Dvexpress-v2m-rs1.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 * V2M-P1
8 * HBI-0190D
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
14 * original variant (vexpress-v2m.dtsi), but there is a strong
18 * CHANGES TO vexpress-v2m.dtsi!
20 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 v2m_fixed_3v3: fixed-regulator-0 {
24 compatible = "regulator-fixed";
25 regulator-name = "3V3";
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/freebsd/sys/dev/pms/RefTisa/sallsdk/spc/
H A Dsainit.c2 *Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved.
55 bit32 gFPGA_TEST = 0; // If set unblock fpga functions
66 * \param usecsPerTick micro-seconds per tick for the LL layer
69 * \return -void-
105 memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength = sizeof(agsaLLRoot_t); in saGetRequirements()
106 memoryRequirement->agMemory[LLROOT_MEM_INDEX].numElements = 1; in saGetRequirements()
107 memoryRequirement->agMemory[LLROOT_MEM_INDEX].totalLength = sizeof(agsaLLRoot_t); in saGetRequirements()
108 memoryRequirement->agMemory[LLROOT_MEM_INDEX].alignment = sizeof(void *); in saGetRequirements()
109 memoryRequirement->agMemory[LLROOT_MEM_INDEX].type = AGSA_CACHED_MEM; in saGetRequirements()
113 memoryRequirement->agMemory[LLROOT_MEM_INDEX].singleElementLength, in saGetRequirements()
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