Lines Matching +full:fpga +full:- +full:region
1 // SPDX-License-Identifier: GPL-2.0
4 /dts-v1/;
6 #include "aspeed-g5.dtsi"
7 #include <dt-bindings/gpio/aspeed-gpio.h>
8 #include <dt-bindings/interrupt-controller/irq.h>
12 compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
26 compatible = "shared-dma-pool";
37 stdout-path = &uart5;
41 compatible = "gpio-leds";
51 iio-hwmon {
52 compatible = "iio-hwmon";
53 io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
61 m25p,fast-read;
63 #include "openbmc-flash-layout.dtsi"
69 pinctrl-names = "default";
70 pinctrl-0 = <&pinctrl_spi1_default>;
73 m25p,fast-read;
75 spi-max-frequency = <100000000>;
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_rmii1_default>;
86 clock-names = "MACCLK", "RCLK";
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_txd1_default
107 pinctrl-names = "default";
108 pinctrl-0 = <&pinctrl_adc0_default
117 gpio-line-names =
118 /*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","",
119 /*B0-B7*/ "","","","","","","","",
120 /*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","",
121 /*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S",
123 /*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN",
125 /*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP",
127 /*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0",
128 "P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","",
129 /*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3",
131 /*I0-I7*/ "","","","","","","","",
132 /*J0-J7*/ "","","","","","","","",
133 /*K0-K7*/ "","","","","","","","",
134 /*L0-L7*/ "","","","","","","","",
135 /*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN",
138 /*N0-N7*/ "","","","","","","","",
139 /*O0-O7*/ "","","","","","","","",
140 /*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT",
144 /*Q0-Q7*/ "","","","","","","","",
145 /*R0-R7*/ "","","","","","","","",
146 /*S0-S7*/ "","","","","","","","",
147 /*T0-T7*/ "","","","","","","","",
148 /*U0-U7*/ "","","","","","","","",
149 /*V0-V7*/ "","","","","","","","",
150 /*W0-W7*/ "","","","","","","","",
151 /*X0-X7*/ "","","","","","","","",
152 /*Y0-Y7*/ "","","","","","","","",
153 /*Z0-Z7*/ "","","","","","","","",
154 /*AA0-AA7*/ "","SENSOR THERM","","","","","","",
155 /*AB0-AB7*/ "","","","","","","","",
156 /*AC0-AC7*/ "","","","","","","","";
169 //FPGA
251 aspeed,lpc-io-reg = <0x60>;
256 aspeed,lpc-io-reg = <0x62>;
261 aspeed,lpc-io-reg = <0xCA2>;
266 aspeed,lpc-io-reg = <0x97DE>;
271 snoop-ports = <0x80>, <0x81>;
281 aspeed,lpc-io-reg = <0x3f8>;
282 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_pwm0_default
299 aspeed,fan-tach-ch = /bits/ 8 <0x00>;
304 aspeed,fan-tach-ch = /bits/ 8 <0x01>;
309 aspeed,fan-tach-ch = /bits/ 8 <0x02>;
314 aspeed,fan-tach-ch = /bits/ 8 <0x03>;
319 aspeed,fan-tach-ch = /bits/ 8 <0x04>;
324 aspeed,fan-tach-ch = /bits/ 8 <0x05>;
329 aspeed,fan-tach-ch = /bits/ 8 <0x06>;
334 aspeed,fan-tach-ch = /bits/ 8 <0x07>;
340 memory-region = <&video_engine_memory>;