Lines Matching +full:fpga +full:- +full:region
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Paul Kocialkowski <paul.kocialkowski@bootlin.com>
16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
18 Because the controller is intended for use in a FPGA, most of the
20 synthesis time. As a result, many of the device-tree bindings are meant to
24 Layers are declared in the "layers" sub-node and have dedicated configuration.
32 - xylon,logicvc-3.02.a-display
33 - xylon,logicvc-4.01.a-display
42 clock-names:
46 - const: vclk
48 - enum:
49 - vclk2
50 - lvdsclk
51 - lvdsclkn
52 - enum:
53 - vclk2
54 - lvdsclk
55 - lvdsclkn
56 - enum:
57 - vclk2
58 - lvdsclk
59 - lvdsclkn
64 memory-region:
67 xylon,display-interface:
70 - parallel-rgb
71 # ITU-T BR656 interface (C_DISPLAY_INTERFACE == 1)
72 - bt656
73 # 4-bit LVDS interface (C_DISPLAY_INTERFACE == 2)
74 - lvds-4bits
75 # 3-bit LVDS interface (C_DISPLAY_INTERFACE == 4)
76 - lvds-3bits
78 - dvi
81 xylon,display-colorspace:
84 - rgb
86 - yuv422
88 - yuv444
91 xylon,display-depth:
95 xylon,row-stride:
103 xylon,background-layer:
109 xylon,layers-configurable:
119 "#address-cells":
122 "#size-cells":
126 "^layer@[0-9]+$":
133 xylon,layer-depth:
137 xylon,layer-colorspace:
140 - rgb
142 - yuv
145 xylon,layer-alpha-mode:
147 # Alpha is configured layer-wide (C_LAYER_X_ALPHA_MODE == 0)
148 - layer
149 # Alpha is configured per-pixel (C_LAYER_X_ALPHA_MODE == 1)
150 - pixel
153 xylon,layer-base-offset:
159 xylon,layer-buffer-offset:
163 layer base offset for the second buffer used in double-buffering.
165 xylon,layer-primary:
174 - reg
175 - xylon,layer-depth
176 - xylon,layer-colorspace
177 - xylon,layer-alpha-mode
180 - "#address-cells"
181 - "#size-cells"
182 - layer@0
188 sub-nodes that each describe a registered layer.
198 - compatible
199 - reg
200 - clocks
201 - clock-names
202 - interrupts
203 - xylon,display-interface
204 - xylon,display-colorspace
205 - xylon,display-depth
206 - xylon,row-stride
207 - layers
208 - port
211 - |
212 #include <dt-bindings/interrupt-controller/irq.h>
215 compatible = "xylon,logicvc-3.02.a", "syscon", "simple-mfd";
218 #address-cells = <1>;
219 #size-cells = <1>;
222 compatible = "xylon,logicvc-3.02.a-display";
225 memory-region = <&logicvc_cma>;
228 clock-names = "vclk", "lvdsclk";
230 interrupt-parent = <&intc>;
233 xylon,display-interface = "lvds-4bits";
234 xylon,display-colorspace = "rgb";
235 xylon,display-depth = <16>;
236 xylon,row-stride = <1024>;
238 xylon,layers-configurable;
241 #address-cells = <1>;
242 #size-cells = <0>;
246 xylon,layer-depth = <16>;
247 xylon,layer-colorspace = "rgb";
248 xylon,layer-alpha-mode = "layer";
249 xylon,layer-base-offset = <0>;
250 xylon,layer-buffer-offset = <480>;
251 xylon,layer-primary;
256 xylon,layer-depth = <16>;
257 xylon,layer-colorspace = "rgb";
258 xylon,layer-alpha-mode = "layer";
259 xylon,layer-base-offset = <2400>;
260 xylon,layer-buffer-offset = <480>;
265 xylon,layer-depth = <16>;
266 xylon,layer-colorspace = "rgb";
267 xylon,layer-alpha-mode = "layer";
268 xylon,layer-base-offset = <960>;
269 xylon,layer-buffer-offset = <480>;
274 xylon,layer-depth = <16>;
275 xylon,layer-colorspace = "rgb";
276 xylon,layer-alpha-mode = "layer";
277 xylon,layer-base-offset = <480>;
278 xylon,layer-buffer-offset = <480>;
283 xylon,layer-depth = <16>;
284 xylon,layer-colorspace = "rgb";
285 xylon,layer-alpha-mode = "layer";
286 xylon,layer-base-offset = <8192>;
287 xylon,layer-buffer-offset = <480>;
292 #address-cells = <1>;
293 #size-cells = <0>;
297 remote-endpoint = <&panel_input>;